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Designing DDR3 SDRAM controllers with today's FPGAs
The recently introduced DDR3 SDRAM technology paves the way to higher data rates (from 800 Mbps to 1600 Mbps) and provides higher performance for many systems that depend on data, video, or packet processing.
Every architectural change for higher performance comes at a price, however, and one aspect is measured in additional man hours of system design time, simulation, and troubleshooting. DDR3 SDRAM is an evolutionary step from DDR2 and provides enhanced features to enable higher data rates. It also maintains enough backward compatibility with DDR2 to provide system designers with the benefit of not having to reinvent the wheel on all aspects of controller and interface design.
In the case of FPGA-based designs, some FPGA vendors have taken on the task of designing a complete controller and physical layer interface. This article outlines the major differences between DDR3 and DDR2 SDRAM architecture, the challenges that come with architectural changes for higher data rates, and also reviews them in the context of a Xilinx Virtex-5 FPGA reference design tested in hardware at 800 Mbps. The reference design is available free for downloading.
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