By Nelson Seiden, Knowlent CorporationJanuary 07, 2008 -- edadesignline.com
Analog-mixed signal designers need a first-time right design methodology now. Why is this familiar cry more urgent and probably truest this time? After all, we've heard EDA industry pundits and users raise the clarion call before.
In the last 18 months, the explosive growth of portable (and ever smarter) cell phones, GPS systems and multi-media devices has provided electronics suppliers with the potential for incredible growth. But with the increase in market opportunity come equally accelerated pressures to deliver high performance, low power, and reliable solutions much faster than before, and at continually shrinking ASPs.
This new analog-mixed signal design imperative is challenged by ever-shorter development schedules, increasing price pressures, smaller geometry foundry processes (which yield lower cost chips in mass volumes) with increasingly-magnified up front development costs and the absolute need for first-time-right design methodology.
As a result, semiconductor companies are compelled to put more technology on a single chip creating much higher potential for error than ever before. Of overwhelming concern is the risk of multiple silicon spins to get to a production-worthy product and create a design that will yield enough good parts per wafer to justify the investment in the smaller geometry process.
For this reason, semiconductor companies are facing the challenge of developing an analog/mixed-signal first-time-right methodology. Analog designs are notoriously sensitive to variations in temperature, noise and process variation, much more so than digital. These analog designs must be thoroughly verified against these variations and then analyzed within the context of the SOC after it is characterized at the block level.
Today, the process of developing test benches, characterizing designs and releasing them to the foundry are the responsibility of the design team. In most cases, designers work independently on various blocks and make the decision as to which analyses to run, what parameters to test and when to declare that the design is ready to be integrated. The design team shares very little knowledge IP; and without a standard flow that checks compliance at various stages in the analog design flow, very little design IP is reused.
The analog designer decides which parameters should be followed, but in the final days before tape out, there isn't time to rerun all of the analyses. Therefore, it is up to the engineer to determine what subset of tests should be run.
From the designer's perspective, very little has changed in the tools to do his job. In very specific cases, new SPICE simulators are performing 3, 5 and even 10 times faster than the designer's legacy tools. In general, however, their applicability is targeted and overall simulation time is not significantly reduced. In general, new tools to make designers significantly more effective have not been widely available.
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