Update: Cadence Completes Acquisition of Cosmic Circuits (May 23, 2013)
Krishnan Ramabadran, Vice-President - Marketing, Cosmic Circuits
Those who have been observing last year’s activity in the analog IP space would readily infer the growing relevance and importance of Analog IP to the semiconductor development eco-system. Interestingly, the digital world needs more analog, and a healthy Analog IP eco-system is a critical enabler to innovation at the system-on-chip level.
Today’s high cost of SoC development requires quality analog-IP cores to minimize the risk to the development programs. And the complexity and feature-performance of analog-IP has been a constantly rising bar. The industry has been demanding more from the analog-IP providers. The fact that Analog-IP has been thriving and growing since the advent of the system-on-chip era goes to show that the providers of analog IP have been successful in rising up to the demands. However, the changing technology landscape and end-customer (the users of electronic equipment) demands, poses newer challenges.
In this background, it is interesting and instructive to look at some of these trends and the new technology challenges that need to be tackled by the analog-IP providers to keep the SoC designer community happy in the nanometer era (the 90nm, 65nm and 45nm nodes, and beyond).
Shrinking Voltage levels
What was 1.8V “low-voltage” core in 0.18um node, has now hit 1.0V and below with 65nm and beyond. And the IO supply voltage has shrunk from 3.3V (0.18um) through 2.5V to 1.8V (65nm and below).
Analog architectures that rely on the higher IO voltages traditionally relied heavily on the IOtransistor. However, analog architectures that make use of the higher “performance” of the digital transistor necessarily have to accommodate the lower supply voltages. The challenge has become one of innovating on architectures and circuit topologies that take advantage of the coretransistor and operate off the smaller core supply voltage. Architectures that successfully accomplish this provide lower power consumption.
Analog circuit blocks that use the core transistor face the challenge of transistor leakage due to the smaller geometries. While clever architectures take advantage of the “speed” and the better “trans-conductance” of the core transistors, nanometer technologies throw up the additional challenge of leakage.
For the present discussion, leakage is primarily of two kinds: (a) Gate-leakage (b) Ioff (channel leakage). Mixed-signal designs hold the “analog-value” as charge on a capacitor, and leakage of charge leads to inaccuracies.
The analog designer is challenged with factoring these aspects into the architecture and circuit topology selection. This requires significant innovation and careful design.
Good old cost of chip
The system-on-chips in the nanometer era often times actually carry not just one, but multiple systems on a chip. Take the case of a portable gadget SoC that may require a couple of wireless connectivity options such as wireless LAN and Bluetooth, and audio processing system, a connectivity option such as USB, power-management, peripheral control, application or video/image processor, perhaps a GPS system, and such. Many of these “sub”-systems require analog, and say, in 65nm.
If the analog IP-cores that are integrated were to be of previous generation architectures, and not take advantage of the capabilities offered by nanometer technologies, the system designer would quickly find that the analog has saddled the chip with a significant die-area, and that on a 65nm chip, perhaps undoing the benefits of digital-shrink offered by the process node. Increasing levels of systems-on-chip integration with increasing analog integration calls for careful attention to the die foot-prints of the analog cores, if the size optimization of the digital section of the chip are to be preserved at the full-chip level.
Innovation to keep the analog IP foot-print low is necessary to ensure that we, the endconsumers, get the gadgets into our pockets while not pinching our purses.
Form-factor and system-BOM integration
Portable consumer and communication is clearly driving miniaturization. Multi-function chips are becoming more common. Gadgets often have a single system-on-a-chip and the rest are powerregulators and passive on the board. While analog integration is main-stream, RF integration is becoming more common. Larger capacities of RAM are being integrated on-chip, and flash memory as well, in increasing circumstances.
A hitherto uncommon choice - that of integrating power regulators on system-on-chips, is gaining popularity among chip-architects. The availability of power-regulator cores as IP from analog IP companies like Cosmic Circuits (that offers a wide portfolio with different silicon tested power regulators in 130nm, 90nm and 65nm) has been an enabler and catalyst for this trend. Powerregulator IP-cores that connect to a Li-Ion battery or a USB power supply directly are available now. With a variety of power-supply requirements for a system (multiple core supplies, analog supply, RF supply, peripheral supplies, voltage islands, and so on), the PCB real-estate as well as the system BOM cost other than the system-on-chip is increasing. Thankfully, availability of power-regulators as IP has started positively impacting this aspect.
Several technology innovations are being driven by the need to extend battery life in portables. To state a few: low-leakage semiconductor processes, low-K dielectrics, dropping voltage levels, dynamic voltage management techniques, new tools for power-optimization at various levels of the design cycle, etc. Reducing power-consumption in analog IP is no exception.
With analog to digital converters, traditional theory indicates that the scaling down of supply voltages forces usage of larger internal capacitors to store charge, to preserve the same performance. It requires innovative techniques that are digital-nanometer-process friendly to beat or work-around these limitations to offer lower power consumption levels.
Take the case of a MIMO WiFi (802.11n) or WiMax (16e) solution for portable applications – this requires a significant amount of parallel analog channels that can all add up to a significant power number, while the digital section is low power due to the nanometer process. If analog were not to utilize the capabilities of the faster transistors, a higher power across all analog blocks can quickly offset the benefit of lower power-dissipation of a 65nm technology node.
We are right in the middle of a technology scene where interface speeds requirements are high, but bottlenecked due to limitations in cost-effective package pin-outs. Use of high-speed LVDS interfaces and SERDES for chip-to-chip communication is becoming main-stream. The LVDS interfaces sued in mobile applications have increasingly got to be low in power and faster too. Having recognized this trend, standards are playing an active role here. High-speed chip-to-chip interfaces are necessary, but peripheral, to a system-on-chip. It is the analog IP provider that is increasingly being relied on for this. To the gigahertz bit-rate requirement, add lowering of supply voltages and requirement of low-power in mobile applications, and analog IP companies come to the rescue of the SoC chip designer.
The nanometer technologies are requiring several Design-For-Manufacturing aspects to be adhered to. Sensitive analog can be impacted by not following DFM techniques. For example, “dishing” (the thinning of the metal levels across the wafer forming a dish due to more thinning at the centre than the periphery) and local metal density differences can cause mismatch between matched-capacitors. What is visually m
atched is not electrically matched. Sophisticated extraction and careful simulation is essential. In general, architectures that require a fewer number of components that ought to be matched are more DFM friendly. For, example, a fewer number of stages in a pipeline A/D converter is an advantage. Architectures that rely on comparators than on amplifiers are preferable. Proximity effects are more prominent in 65nm and below and need to be comprehended in the careful layout of the analog circuits.
A number of flavors of a process-node that are offered by the foundries are increasing. For example, a low-leakage flavor of the process for handheld applications, a higher-speed version for speed critical processor applications, different IO voltages such as 3.3V, 2.5V and 1.8V, are common nowadays.
While analog circuit blocks are inherently “non-portable” as their digital counter-parts, portability in the context of analog can be defined as the elegance of a circuit block. It is often an indication of the amenability of the circuit block to design/simulation tools and automation. All of this would imply a robust architecture and design implementation and ultimately lower-risk and better yields in production.
The Analog IP providers serving the important purposes of shortening the time-to-market and reducing risk for system-on-chips, need to look choose architectures that are elegant (“portable”). Architectures that utilize more digital techniques and the speed of the transistor are more elegant than ones that use a number of sensitive amplifiers. Such solution providers often are able to test their solution across process flavors, thus increasing the robustness and confidence in the solution. The SoC design community is benefited in having analog IP available at the right time, and move quickly from system innovation to system-on-chip solutions.
The shape of things to come
Necessity being the mother of invention, the analog IP community already is keeping pace with the challenge. Cosmic Circuits, an Analog IP company that offers a portfolio of analog IP cores in 130nm, 90nm and 65nm, had its engineers take a fresh look at creating architectures for the nanometer era.
Take the case of the MIMO analog front end from the company. A multi-channel front-end can quickly saddle the SoC with a large foot-print on the die and take up a good fraction of the chip power-budget. However, the choice of right architectures has helped achieve a 40-45% reduction in area going into 65nm, from the industry’s 130nm solution. Similarly, a good 40-45% reduction in receive-power has been achieved with the choice of right architectures. Usage of minimal number of amplifiers and digital nanometer friendly architectures has helped achieve operation with low core supply voltages and an elegance and better tractability for porting across process flavors.
Take the case of the 12-bit 205MSPS A/D converter from the same company, built to the 130nm node for SoC integration. Utilizing an optimized low-amplifier count pipeline ADC technology and working off a low supply voltage of 1.2V for the entire ADC, the size and the power-consumption have been dramatically cut.
Analog IP providers have to offer newer and more effective ways of system-cost reduction to SoC companies. For example, Switching and Linear power-regulators for SoC integration effectively serves this purpose. When optimized for portable electronics, the integration of these IP-cores reduces not only the BOM cost and the form-factor, but also improves power-efficiency by making the application of techniques like Dynamic-Voltage-Management easier. IP companies such as Cosmic Circuits have been providing a portfolio of such IP in nanometer technology nodes and serving this space.
Cosmic Circuits builds on its core-technology and grooms a culture of innovation. The innovative architectures that it evolves, aims to address all the aspects discussed above. The jump from 1.8V (0.18um) to 1.0V (65nm or 45nm and beyond) requires new thinking – new architectures. It would be a quick short-cut to stick to legacy architectures; only till system-on-chip architects find that the analog IP actually weighs too heavy on power cost or battery-life, integration or miniaturization.
The analog IP scene has been brightening up, with the focus on analog cores optimized for the nanometer technologies from companies such as Cosmic Circuits. With increasing levels of analog IP integration on system-on-chips, and with more discerning chip-architects, the demand for optimized analog IP continues to grow and transform the analog IP scene in the nanometer era. Cosmic Circuits is aptly positioned at this inflexion.