By Alain Raynaud, EVE
(02/12/08, 11:57:00 AM EST) -- EE Times
After years discussing verification strategies with hundreds of ASIC designers, it finally hit me: We're at the point where designers are trying to manage billions of cycles of simulation.
Take the video chip business where H.264 and high- definition TV are hot. These chip designers need to simulate hundreds of conformance streams to make sure that the chip is ready to ship. In the wireless handheld market, firmware is key. Ultimately, the device must boot Linux and run a Java application on its LCD screen. And, designers of network routers need to stress their chips through pseudo-random traffic to benchmark key performance metrics, such as packet drop rate.
All these tasks have one thing in common: they require billions of cycles of simulation. Until a designer realizes that he or she can't manage billions of cycles like any other simulation, they hit a wall that I call the "Billion-Cycle Challenge."
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