Tom Anderson, Cadence Design Systems(02/27/2008 9:32 AM EST) -- EE Times
The power architectures on today's power-cycled system-on-chip designs can be distressingly complex. Multiple power domains with many power modes require a thorough verification process.
Five technologies " PDML specification, power-aware simulation, structural power checks, power-related assertions and formal analysis of the power control logic " provide outstanding checking and coverage while shaving half the power verification time. These technologies are the key components of an effective power verification methodology to ensure that low-power design produces high-confidence chips.
In today's power-cycled systems-on-chip (SoCs), the power budget is lowered by reducing or shutting off power to regions of the device known as power domains. First-generation power-cycled SoC designs have only a few power domains, but newer designs now under development will feature as many as 20, producing numerous power modes.
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