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32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Multicore systems-on-chip can handle embedded designs
Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
Grant Martin and Steven Leibson, Tensilica(02/26/2008 5:05 AM EST) -- EE Times
Many design problems are conveniently concurrent and are easy to attack with multiple processor cores, though not necessarily using a symmetric multiprocessing (SMP) architecture. Big semiconductor and server vendors currently offer SMP multicore processors, which are good for solving certain kinds of design problems. And large servers and server farms support applications such as Web query requests that follow a SAMD model: single application, multiple data (an over- simplification, perhaps, but a useful one).
SAMD applications date to early, proprietary mainframe networks used for certain big applications such as real-time airline reservation and check-in systems or real-time banking. These applications are particularly suitable for SMP multicore processors: They essentially run the same kind of code, they do not exhibit data locality, and the number of cores running the application makes no material difference other than speed.
A large number of homogeneous, cache-coherent processors organized into SMP clusters seems a reasonable technology to apply to such applications, and multicore chips and servers from Intel, Advanced Micro Devices, Sun, IBM and others seem a reasonable way to exploit the inherent parallelism needed to satisfy many simultaneous user requests. Other applications, such as packet processing, may also be able to exploit SMP multicore or multiprocessor systems. SMP is simply not a good processing model for many embedded systems, however, because it eases the processor designer's task of creating a multiple-processor system but makes poor compromises in terms of power consumption, heat dissi- pation and software development requirements.
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