Useful design patterns for building embedded multicore systems
February 26, 2008 -- dspdesignline.com
Consolidation is a long-standing trend within the embedded world. It enables more capable, higher-performance embedded devices using fewer components, at lower cost and power budgets.
The latest round of this trend is the proliferation of multicore embedded microprocessors, offering multiple processor cores in a single package " with lower power consumption and cost than an equivalent single-core processor.
Taking advantage of multiple processor cores will require more system-level design cooperation between software and hardware teams. In that spirit, here are high-level overviews of three simple models for multicore systems which are straightforward to implement with today's tools and hardware.
These multicore design patterns are not intended to be rigid models for exactly specifying a system. Rather, they are starting points for thinking and talking about the high-level picture of what your system does, and provide a common terminology so that hardware and software teams can hash out a multicore system structure.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related Articles
- Meeting Increasing Performance Requirements in Embedded Applications with Scalable Multicore Processors
- Programming heterogeneous multicore embedded SoCs
- Building eye-catching GUIs for your embedded MCU designs
- Building more secure embedded software with code coverage analysis
- Building high performance interrupt responses into an embedded SoC design
New Articles
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
Most Popular
- System Verilog Assertions Simplified
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Optimizing Analog Layouts: Techniques for Effective Layout Matching
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)