Juergen Jaeger, Synplicity (03/10/2008 4:33 AM EDT), EE Times
ASIC, ASSP and SoC development is, and will always be, a risky and expensive business. Add to this the fact that today functional verification constitutes 50 to 70 percent of the development effort, and it becomes obvious that traditional verification methodologies are no longer by themselves sufficient to keep up with growing design complexities and shrinking design cycles.
Prototyping, because of its unparalleled verification performance and ability to act as a software development platform, is one of the fastest-growing verification methodologies. And although virtually every ASIC, ASSP and system-on-chip developed today is prototyped on an FPGA board, many still consider prototyping an ad hoc methodology rather than a mature verification solution.
That perception has some validity to it, because there is still a lot of "assembly required" to make a custom prototype board work successfully. But only prototyping offers the performance, flexibility and capabilities necessary for mastering some of the most critical verification challenges facing designers today. As a result, FPGA-based prototyping is quickly evolving, "growing up" in ways that allow it to address these challenges. FPGA-based prototyping is turning into a highly productive, easy-to-use verification methodology.
FPGA-based prototyping has been around for quite a while; but not until very recently, with the advent of a new generation of high-performance and high-density FPGAs, did prototyping become suitable for verification of virtually every ASIC, ASSP and SoC design. Today's high-density devices offer core speeds in the hundreds of megahertz and complexities of up to 2 million (ASIC) gates.
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