By Chris Allsup, Synopsys, Inc.
March 18, 2008 -- edadesignline.com
The very process of testing digital circuits routinely increases their dynamic power consumption to levels far exceeding their power specification. If the power consumption is great enough, it can result in failures at wafer probe or pre-burn-in package test that require a significant amount of time and effort to debug. This issue, especially prevalent when testing very large systems-on-a-chip (SoCs) under corner conditions, causes unnecessary yield loss on the production line and ultimately reduces manufacturers' gross margins. The best way to avoid test power problems is to incorporate power-aware testing techniques in the design-for-test (DFT) process. In this article, we'll first examine the relationship between dynamic power consumption and test to determine why managing power is more critical today than ever before. Then we'll explore two distinct DFT methodologies that take advantage of recent advances in automatic test pattern generation (ATPG) technology to automate generation of low-power manufacturing tests.