By Mark Goode, ViASIC
(03/26/08, 10:26:00 AM EDT), Programmable Logic DesignLine
Design readiness enables companies to respond quickly to design needs, but how can its true cost be determined? And which solutions – Full Custom ASIC, FPGA, or Structured ASIC – are optimal for a given situation?
Although management and marketing often dictate that the engineering design department must be flexible and responsive, measuring the flexibility of a department is illusive at best. One way to start is by creating a valid metric for design response time, which can be used to help evaluate potential improvements and determine which ones are effective.
For example, is it important to be one day, one week, or one month earlier to market? The answer would seem to be an obvious "yes," and without the context of cost it would be an easy decision. But how much would it cost to shave off a few days from engineering design response time, and would that be that a good investment? Under certain circumstances, in low- and medium-volume situations, it is possible over the lifetime of a design to reduce the time to market and/or production time without incurring additional costs.
ViASIC, which makes EDA software for via-configurable Structured ASIC solutions, and Sandia National Labs have performed similar analysis to determine the cost of "design readiness." The results are particularly decisive because of the added time in the critical production path attributed to radiation and other harsh environment qualification. This analysis enables measured decisions regarding the cost of design readiness in full custom ASIC solutions, FPGAs, or structured ASIC solutions.
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