By Bob Cox, Virtium TechnologyEmbedded.com (04/12/08, 07:26:00 PM EDT)
The power struggle between DDR2 and DDR3 continues the tradeoff game between bandwidth and latency. The timing shifts required by the DDR3 flyby topology change the time at which byte lanes demand power by utilizing additional Delay Lock Loop within the controller itself. More DLL's require more power and generate heat as a byproduct.
As the shifts in timing for read and writes are spread out, the demand for power over time dramatically reduces the impact on instantaneous demand on SSO. This is a definite advantage for the memory module where memory reads are generated. DDR3 also introduces a lower voltage further reducing power consumption.
The demand for low power in embedded applications has finally been echoed in the voices at the standards organizations. As the voltage levels for memory devices are reduced, the difference in absolute value between the core voltages and interconnect voltages has become smaller and smaller.
Since power consumption relates directly to core voltage, the reduction in power consumption from generation to generation of DRAM memory is rapidly diminishing.
The problem grows as we look into the arena of stacking components or stacking die into packages where thermal dissipation plays a predominant role; next generation generally means larger die size and more transistors consuming more power and generating more heat.
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