Update: Exar Corporation Acquires Altior Inc. to Provide Additional Growth in Data Compression (February 19, 2013)
By V. A. Chouliaras, Loughborough University, and Chad Spackman, CTO, CebaTech Inc.
Programmable architectures, including micro-coded data-parallel accelerators, are the backbone processing engines in high performance ASICs. Traditionally, such architectures have been implemented at register transfer level (RTL), as this level of abstraction is sufficiently close to the actual hardware architecture and is fully supported by the mainstream ASIC and FPGA synthesis flows.
With the introduction of disruptive electronic system level (ESL) synthesis tools such as CebaTech Inc.'s C2R Compiler, large scale accelerators can be described at a higher abstraction level. At the same time, the processor architect maintains full control over the ESL synthesis process by using advanced features such as precise interface inference, user-specified clocking, explicit data (DLP) level and thread (TLP) level parallelism as well as combinatorial logic.
This article elaborates on the use of the C2R compiler for implementing a 2-way LIW/SIMD hybrid accelerator, attached to a scalar processor core, with configurable micro-architecture and programmer's model/ISA. The accelerator was designed for the ITU-T G723.1 and G729.A speech coding standards.
Click here to read more ...