English
Asynchronous DSPs: Low power, high performance
By James Awad, Octasic
May 01, 2008 -- mobilehandsetdesignline.com
An asynchronous DSP offers better power, performance, and reliability than one based on standard synchronous logic. It also enables simpler and less expensive PCB and power supplies.
Until today, the performance of a processor has primarily been measured by the speed of its clock. The vast majority of integrated circuit (IC) designs have been based on a synchronous architecture, which is governed by a global clock. This architecture has become so ubiquitous that it is considered by many to be the only way to design digital circuits. There is, however, an altogether different design technique that is just now coming to the forefront: asynchronous design.
The main driver for this is the state of silicon technologies. As silicon geometries shrink below 90 nanometers, power reduction has become the top priority. Because asynchronous design offers lower power and more reliable circuits, it has been proposed as a way to address this requirement.
Asynchronous design has been avoided in the past for many reasons, the most important being the lack of a standardized tool flow. To deliver devices quickly, IC design teams use high-level programming languages in combination with electronic design automation (EDA) tools that speed tasks such as logic design. If such tools were available for asynchronous design, we would likely see more devices with asynchronous logic components.
In the past, most asynchronous designs were small circuits used to complement synchronous circuits. Larger asynchronous devices have appeared recently, but these devices often targeted niche markets such as embedded sensors.
We believe that the opportunities for asynchronous logic are far greater than past devices suggest. In this article we make the case for a general purpose digital signal processor (DSP) core based entirely on asynchronous logic. We reveal many benefits, both for the IC designer and the end user.
May 01, 2008 -- mobilehandsetdesignline.com
An asynchronous DSP offers better power, performance, and reliability than one based on standard synchronous logic. It also enables simpler and less expensive PCB and power supplies.
Until today, the performance of a processor has primarily been measured by the speed of its clock. The vast majority of integrated circuit (IC) designs have been based on a synchronous architecture, which is governed by a global clock. This architecture has become so ubiquitous that it is considered by many to be the only way to design digital circuits. There is, however, an altogether different design technique that is just now coming to the forefront: asynchronous design.
The main driver for this is the state of silicon technologies. As silicon geometries shrink below 90 nanometers, power reduction has become the top priority. Because asynchronous design offers lower power and more reliable circuits, it has been proposed as a way to address this requirement.
Asynchronous design has been avoided in the past for many reasons, the most important being the lack of a standardized tool flow. To deliver devices quickly, IC design teams use high-level programming languages in combination with electronic design automation (EDA) tools that speed tasks such as logic design. If such tools were available for asynchronous design, we would likely see more devices with asynchronous logic components.
In the past, most asynchronous designs were small circuits used to complement synchronous circuits. Larger asynchronous devices have appeared recently, but these devices often targeted niche markets such as embedded sensors.
We believe that the opportunities for asynchronous logic are far greater than past devices suggest. In this article we make the case for a general purpose digital signal processor (DSP) core based entirely on asynchronous logic. We reveal many benefits, both for the IC designer and the end user.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- A High Density, High Performance, Low Power Level Shifter
- Building a multi-voltage, high performance, ultra low standby power 32-bit MCU
- A Flexible, Low Power, High Performance DSP IP Core for Programmable Systems-on-Chip
- High-Performance DSPs -> AltiVec power: PCI buses fall short
- High Speed, Low Power and Flexibility Drive DisplayPort's Increasing Popularity
New Articles
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
- Embracing a More Secure Era with TLS 1.3
- New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI
- Maximizing ESD protection for automotive Ethernet applications