EnglishCLICK - The universal solution of power gating for the whole SoC
Analysis: Altera jumps to 40 nm with Stratix IV
By BDTI
June 05, 2008 -- dspdesignline.com
Altera has unveiled its next-generation high-performance FPGA family, the Stratix IV, and announced that the family will be fabbed in a 40 nm TSMC process. The new Stratix IV chip family will include 12 members: six GX devices, and six E devices. GX chips have from 8-48 high-speed serial transceivers, while the E devices have no transceivers but more memory and more DSP-oriented features. The highest capacity Stratix IV chips will have roughly double the logic capacity of the biggest Stratix III chips—up to 680K logic elements. The new chips will also include up to 22.4 Mbits of internal RAM. Pricing has not yet been announced.
June 05, 2008 -- dspdesignline.com
Altera has unveiled its next-generation high-performance FPGA family, the Stratix IV, and announced that the family will be fabbed in a 40 nm TSMC process. The new Stratix IV chip family will include 12 members: six GX devices, and six E devices. GX chips have from 8-48 high-speed serial transceivers, while the E devices have no transceivers but more memory and more DSP-oriented features. The highest capacity Stratix IV chips will have roughly double the logic capacity of the biggest Stratix III chips—up to 680K logic elements. The new chips will also include up to 22.4 Mbits of internal RAM. Pricing has not yet been announced.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Altera Stratix IV User Guide Lite
- A 66-mW 3.4Gbps Transmitter PHY for HDMI Applications in 2.5V 40-nm CMOS
- Altera courts ASIC designers with block-based Stratix PLD
- Distorted Waveform Phenomena in 7nm Technology Node and its Impact on Signoff Timing Analysis
- Virtual Prototyping for Fault Analysis, Functional Safety
New Articles
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1
- Pyramid Vector Quantization and Bit Level Sparsity in Weights for Efficient Neural Networks Inference
- Enabling Bluetooth Out-of-Band pairing through NFC
- Advantages and Challenges of Designing with Multiple Inferencing Chips
Most Popular
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1
- Dynamic Memory Allocation and Fragmentation in C and C++
- A Review Paper on CMOS, SOI and FinFET Technology
- Using SystemVerilog Assertions in RTL Code
- Design Rule Checks (DRC) - A Practical View for 28nm Technology