By Mitch Dale, Calypto Design Systemsedadesignline.com (September 09, 2008)
While production schedules keep getting squeezed, managing power consumption takes more of a designer's time. As a result, finding ways to reduce power in chips, while minimizing design-cycle impact, is an area of keen interest. Responding to this need, the electronic design automation (EDA) market segment has produced a number of solutions that offer the potential for noticeable power reduction early in the design flow with minimal schedule impact.
This article describes the efforts to reduce power by a leading supplier of networking and network storage equipment. This company offers a full range of switches and routers to serve the networking needs of businesses, from small companies to global service providers. Previously, new product development focused on higher bandwidth and expanded capabilities, such as security and quality of service. With an increasing emphasis on controlling energy costs, more and more of its customers are demanding improved power efficiency, making low power an important design consideration and competitive advantage.
At the core of the company's products are large system-on-chip (SoC) devices containing dozens of I/O ports that support multiple protocols connected through a high-speed switching matrix. All totaled, these devices incorporate millions of gates.
The engineering challenge is to develop these high-performance devices to consume the lowest power possible under worst-case, peak-loading conditions. This mandates a low-power design flow that scales to million-gate designs and reduces power when designs are fully active. The design flow must work with existing implementation tools and save power without negatively affecting performance or chip area.
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