Bridging the DFT and Product Engineering Gap to Achieve Early Silicon Validation

• A total of 51 lessons learned were identified.
• Three groups within Wireless own the majority of the issues (Top level design / Analog IP design / PE team)

• Unwritten rules : There are a lot of “known” rules that are not spelled out anywhere. The discrepancy between simulated TDL(Test Description Language) and TDL run on tester due to flow limitation/issues results in multiple TDL handoff/QC issues:

1. PLL(Phase Locked Loop) TDL's for VLCT require two clocks, which is not required on any other tester.
2. Pattern set type must be spelled out in order to run VERMI
3. BIST(Built-In Self-Test) TDL's require strobing of DONE signal

• Understanding analog IP setting as per configuration settings in valid state/mode .

1. PLL shutdown requires BYPASS mode
2. Valid mode : Only power on and retention for some subchip/module and no power down mode for IDDQ measurement

• Methodology failures

1. Alert for memories used for functional mode, but not reviewed for test mode.
2. Assumption that some IP did not change from previous version of the project to new version of the project resulted in incomplete review from IP owner (e.g. missing port definition in one of the analog IP causing metal release)

• Documentation

1. Incorrect I/O sheet describing lowest power setting for I/Os: Unnecessary TDL regeneration and debug to achieve quiescent mode power.
2. Incomplete integration specification: missing clock usage description for STA(Static Timing Analysis). This caused major problem with functional fail due to incorrect sdf (Standard Delay Format) annotation resulting in interface level timing issue. Two months of engineering team effort was spent by customer, India, US engineering team to debug /validate the issue with multiple FIB’s (Focused Ion Beam) eventually resulting in MLR (Metal Level Revision). Apparently same issue was already found earlier and fixed in previous version/project but was missed in next/new project.
3. Incomplete description of shutdown mode in PLL documentation: No description that BYPASS is necessary for shutdown. This resulted in multiple TDL handoff and tester debug time to meet the shutdown power requirement as per specification.
4. Improper naming convention for powerdown control in one of the analog IP resulted in incorrect TDL configuration/setting and regeneration/handoff of patterns to PE team.

• First section is rule based utility which implements some of these lessons learned ensuring completeness of DFT closure. It minimizes product engineering issues/re-delivery of TDL's due to incomplete QC/handoff of pattern and overcomes existing flow limitation.
• Second section maintains score based checklist (DFT-PE silicon validation checklist not DFTM) based on these lessons learned highlighting gaps in DFT closure for silicon validation. 100% compliance on mandatory listing ensures minimal issues and early silicon bring-up.
• The last section includes library of useful documents (1page summary/8-D report) from real examples/lessons learned to ensure lessons learned are not lost and zero repeat of mistakes.

• Features:

• Provides set of automated rules implemented from real examples/issues reducing chances of TDL re-delivery.
• Allows the user to select the rules and run it on either individual files or complete directory.
• Provides user with option to view the results and save the final/corrected TDL file.

• Benefits:

• Improves quality of test pattern deliverable and supports early silicon bring up. Minimizes TDL re-delivery by overcoming existing flow limitation and mismatches between VLCT tester and simulation.
  
• Saves time due to manual effort of correcting individual TDL patterns prior to handoff.
  
• Less prone to error since the rules are validated and automated as compared to manual update which is dependent on experience of DFT engineer.
  
• Modular rules structured as functions allowing new rules to be added with ease

• Features:

• Includes list of score based checklist incorporated from past lessons learned/8-D reports.
• Allows users with flexibility to define importance (mandatory/optional) for checklist as per project requirement.
• Summarizes overall score, providing useful insight to the user on improvement areas.
  

• Benefits:

• Ensures past mistakes are not repeated: All lessons learned from past projects are incorporated as part of checklist reducing human error due to change in engineering teams.

• Features:
• Supports interface to acrobat and html viewer (acroread, html) to load internal 8-D report/1-page issue summary from central repository.
• Categorizes each document for easy listing: DFT, PE, SoC design, IP team.
• Supports easy document update to central repository.


• Benefits:
• Promotes usage of best practices from past lessons learned.
• Provides single access point to useful documents to engineering/management team.

• Minimizes issues due to mismatch between VLCT and simulation by providing automated/error free rules to correct the TDL pattern post DFT verification for tester.
• Score based methodology to give useful insight on completeness of QC process.
• Central repository with easy access to list of 8-Dreports/issues providing clear understanding of past issues and promoting best practices.

[1] Joel G . “Closing the TDL QC Loop on VLCT: Design Simulation of VLCT events” in TI Symposium on Test – 2004

[2] Rosal, J “WIBRO/WIMAX Issues” in TI Wireless Management Review, Dallas May 2007.

[3] Stylianos D, Iraklis D and Thanasis O, “A Unified DFT Verification Methodology.” in IPSoC 2005

[4] Siva Y, “Addressing Post Silicon Validation Challenge: Leverage Validation & Test Synergy” in IEEE International Test Conference Oct 25, 2006

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