By Rakesh Reddy, Cypress Semiconductordspdesignline.com (October 01, 2008)
In embedded applications, a reconfigurable architecture is one that allows alteration of its components and interconnections between them. Such alteration might occur over a portion of the system or an entire platform, and all end-states are defined and controlled by the system. When such reconfiguration occurs fast enough and can be executed during runtime, it is called Dynamic Reconfiguration.
Dynamic Reconfiguration allows for better resource utilization by configuring new functions to meet the necessities of the task at hand. It also provides adaptability by allowing a system to alter its structure to solve problems or introduce features that were not anticipated at the time of conception. The architecture of an FPGA chip is ripe for Dynamic Reconfiguration, and developers are now implementing this stratagem in new parts to increase the throughput of their embedded resource.Built for dynamic reconfiguration
The Field Programmable Gate Array or FPGA contains programmable logic blocks and interconnects that can be programmed to perform functions ranging from trivial logic combinations to complex mathematical computations. Only the number of logic blocks that are available in a FPGA limits the type and complexity of computations that it can support at one time.
In a system where all computations do not need to occur simultaneously – which is often the case – the same set of logic blocks can be programmed to work on different calculations at different instances in time. These logic blocks may be reused any number of times as long as the FPGA contains a static resource (built from specific logic blocks) that remains unchanged and monitors the programming of the remaining blocks.
This concept increases the variety of functions that an FPGA can support and allows developers to switch to more affordable components, thus lowering the cost of end products.
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