In multicore SOC architectures, buses are a last resort

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

By Steve Leibson, Tensilica
EE Times (09/29/08, 12:01:00 AM EDT)

The one-processor system model that dominated electronic system design since 1971 is now thoroughly obsolete. Today's SOC designers readily accept the idea of using multiple processors in their complex systems to achieve design goals and use the terms "control plane" and "data plane" to describe how these various on-chip processors are used on the chip. These terms appeared during the Internet and networking boom. At first, they referred to the design of multiple-board networking systems but have now become universal and are suitable for describing many systems, such as audio- and video-encoding/decoding designs that must handle high-speed data and execute complex control algorithms. Processor I/O data rates are as important as computational performance in such systems.

The main processor bus is the sole data highway into and out of most processor cores. Because processors interact with other types of bus masters--including other processors and DMA controllers--and to support SOC architectures employing bus hierarchies, main processor buses feature sophisticated transaction protocols and arbitration mechanisms that enable such design complexity. These protocols and arbitration mechanisms usually require multi-cycle bus transactions that can slow system performance.