By Anis Uzzaman, Patrick Gallagher, and Edward Malloy, Cadence Design Systems, Inc. edadesignline.com (October 06, 2008)
Driven by the expansion of wireless and power-efficient devices and by the marketing requirement to deliver 'green' electronic systems, designers are increasingly employing low power design techniques to manage the growing challenge of functional power dissipation. Until recently, the idea of managing power during manufacturing test has been a secondary concern. But with shrinking geometries and lower voltage thresholds comes an increasing awareness that excessive power consumption during test can have an impact on digital IC reliability, leading to power-driven failures, infant mortality, and false failures at final test. The emergence of these phenomena calls for adoption of specific power management and low power design techniques for manufacturing test.Power Consumption during Functional Mode vs. Test Mode
Several studies show that test mode power consumption in deep submicron devices can be several times higher than power consumption at functional modes. While typical test mode power consumption limits are usually around 2X functional power, in fact power consumption can be much higher, for a variety of reasons.
For instance, simultaneous testing of multiple modules is sometimes implemented to reduce tester costs -- even though in functional operation, it may be impossible to operate more than a few modules at a time. Switching within logic circuits during scan shift, and high switching rates during scan shift/capture, also produces higher power consumption during test. Similarly, fast at-speed capture pulses in transition test patterns can cause unwanted peak power spikes, leading to IR-drop issues. Finally, increasing the frequency of scan shift cycle to reduce test time can also cause unduly high power consumption at the tester.
Other departures from functional power consumption levels result from field test requirements for worst-case functional power; burn-in testing; and high-voltage testing of devices, all of which result in elevated voltages and temperatures, potentially creating negative impacts on both the test outcome and the device's low power circuitry.
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