By D. Singh, N. Sharma, V. Upadhvava, A. Hazra, A. Jain, A. Goel, R. Hakhoo, STMicroelectronics
edadesignline.com (November 03, 2008)Introduction
With the advent of System-on-Chip technology, designs are becoming bigger in size and thus highly complex, time-to-market is becoming critical, and at the same time, RTL methodologies are generally becoming insufficient to fit into this new role. These factors are driving designers to explore new methodologies for early verification of complex IPs (HW as well as SW) as well as complete system. We at STMicroelectronics have set up a design flow that starts with highly abstracted, easier to write models to cycle accurate or RTL models of IP. While moving to lower levels of abstraction, the modeling becomes complex and so does the verification of the IP. Our approach is best suited to this scenario because it permits us to run same test benches/test scenarios in similar environments throughout, hence permitting the reuse of all the test cases and environments across the complete development cycle efficiently.
In the semiconductor industry, the first step in product realization is the development of a prototype of the specification at a higher level of abstraction, commonly in C/C++. Here, SystemC, a C++ library, comes to the rescue. It facilitates a conceptualization of the coexistence of HW and SW designs together. Along with the TLM transport library, which permits interfacing between transaction-level models, SystemC speeds up the overall verification. Another important aspect is the enhanced portability across differently abstracted architectures. The same test setup can be seamlessly used with different abstraction levels of design.
This paper discusses one such methodology. The ultimate goal was to design and implement UWB MAC (Medium Access Layer) IP. For the purpose of architectural exploration, the whole IP was decided to be implemented in SystemC. Various architectures with varying degrees of abstraction level were explored. The overall effort involved was less, simulation speed obtained was good, and the actual SW implementation started very early in the design cycle. The RTL Implementation of this IP was ported to FPGA available with the SPEAr family. The SPEAr provides, in addition to ARM Core and corresponding set of IP, a configurable logic block that allows an incomparable level of flexibility to the user for implementing his/her logic functions. This shortens time to market and also results in unprecedented cost savings.
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