By Jonah Probell
videsignline.com (December 03, 2008)
An experienced designer explains the basics of video processing pipelines. He shows how they resemble classic RISC processor pipelines, and the tradeoffs of Tensilica and Silicon Hive solutions.
Students of computer processor architectures will find the following diagram familiar.
(Click to enlarge)
Figure 1. 7 stage pipelined RISC processor functional block diagram.
This is a functional block diagram of a generic seven-stage pipelined RISC processor. The design achieves maximum performance when the signal propagation delay through each pipeline stage is equal. An imbalance in propagation delay between stages means that one stage requires a slower clock rate than all others. In practice there is only clock for the entire pipeline, so the slow clock requirement of the imbalanced stage slows down the entire design. To speed up this imbalanced stage, the designer should move some of its logic to neighboring pipeline stages.
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