Reimund Wittmann, Ralf Kakerow and Harald Bothe
IP GEN Rechte GmbH, Bochum, Germany
University of Applied Sciences and Arts, Dortmund, Germany
Non-idealities coming along with the increasing degree of integration have made analog IP design a challenging task. The design process for engineering reliable analog IP in selected nanoscale target processes has become very complex and time consuming. Design automation in this area is required urgently. This paper presents a highly portable and configurable Digital Controlled Potentiometer (DCP) IP core which comes along with a novel, mainly automated IP integration and characterization process with excellent porting capabilities. The DCP-IP core is optimized to be used as a DAC and an SAR-ADC in a wide specification range. The architecture is made robust against resistor parameter variations, it takes even advantage of them by applying a statistical averaging approach. Therefore it is able to support resolutions up to 14 bit with guaranteed monotonicity and high linearity. Design optimization is enabled by using a behavioral blocklevel model (Matlab) which can be mapped to individual process profiles and takes various parasitic effects into account. An accurate yield estimation algorithm detects the critical fabrication influence to IP performance in advance. Based on given IP specification and process selection all design views (schematic, layout, behavioral model and verification testbenches) are generated automatically by using executable design descriptions. Design optimization stays an assisted interactive task. Measurement results of rapid integrations in different process technologies will be presented and discussed, especially a 1.2V 14-bit DCP application (65nm standard CMOS) that reaches superior 1LSB INL and 0.15LSB DNL.
Data converters are vital in every modern transmission system by providing the interface between analog and digital domain. The focus in this paper is set on a Digital Controlled Potentiometer IP which can be easily configured into different DAC and ADC architectures that can be set to different speed, resolution and power consumption requirements. Also extremely accurate on-chip references can be created for multiple purposes (e.g. analog built-in-self-test, built-in-selfcalibration, biasing circuits)  .
The described DCP-IP is built of two groups of regularly resistive unit elements. Analog passive devices in nanoscale processes suffer from large device tolerances and from inherent parasitics, which disturb the overall IP performance. Statistical averaging is a valuable approach to create high linearity performance out of locally inaccurate devices, but it comes along with a very high engineering effort and finally a very sophisticated layout, which is not addressable by handcrafted design anymore even if it is very regular .
The presented DCPs have been automatically designed on schematic and layout level using a generic engineering methodology. Generic engineering models allow describing a full custom design process in an executable manner, without restricting and limiting the innovative design process of the designer. A DCP Matlab-Model library and a set of testbenches have been created to utilize statistical averaging and to allow design optimization for the user by considering circuit specification as well as process constraints. Special attention is spent to minimize area and power requirements without reducing operating reliability in the given process environment. The layout view of the IP, relevant for the fabrication process, can be handled as flexible as a schematic and therefore can be directly included into the optimization process by allowing an immediate backannotation of the relevant parasitic  .
The paper is structured into the following sections: In section 2 the DCP topology and the modeling approach is explained in detail. The IP design environment is described in section 3. Measurement results are presented and discussed in section 4.
II. DCP-IP DESCRIPTION AND MODEL SUPPORT 
Fig. 1 shows the block diagram of a DCP. RString1 consists of 2N high precision resistors, providing high accurate reference node voltages. This R-String determines the overall accuracy of the DCP. Therefore the area of each single unit resistor is large to achieve a small standard deviation. Furthermore R-String1 has low-impedance, determining the driving capability of the overall DCP. R-String2 consists of 2N sub chains of 2M-N serial low precision unit resistors (2M unit resistors in total). Each of the single R-String2 sub chains is attached to one R-String1 resistor. The area efficiency of R-String2 can be increased strongly using small unit resistors with poor standard deviation. This DCP topology enables an area and power efficient design, as one R-String of the DCP is fully in charge of overall accuracy and driving capability utilizing traditionally large lowimpedance unit resistors, and the other R-String has relaxed accuracy requirements and provides the needed voltage nodes using very small unit resistors.
Figure 1: M-bit DCP block diagram
The developed Matlab model library supports design optimization and fast block level simulation capability within a system level simulation. Following performance degradation effects are modelled:
Systematic errors: The gradient effect is modelled as well as effects of additional impedances at the connection points between RString1 and R-String2 and at the reversal point of each R-String2 sub chain, which are leading to INL and DNL discontinuities. These systematic errors can be reduced by proper layout.
Statistical errors, based on the normal distributed unit resistors of R-String1 and RString2. These kinds of errors can be reduced utilizing the statistical averaging principle. With other words: By using unit resistors in a compound way the overall accuracy of the compound resistor can be increased. It is therefore possible to buy accuracy (in terms of smaller standard deviation) at the cost of an increase of layout area.
Fig. 2 shows the resistor string configuration used for the presented DCP-IP. For the usecase of a DAC every node of the resistor string has to fulfill the given accuracy requirements. All DCP unit resistors are assumed to be normal distributed.
Figure 2: Structure of the DCP Architecture
Resistance gradients in any direction over the chip layout cause DCP performance degradation. This incident is called gradient effect. Main cause for the gradient effect is the local variation of the square resistance, which depends on the thickness of the resistive material, of the doping profile, etc. Only gradients in direction along the R-String1 (vertical direction in Fig. 2) are critical, as the R-String1 determines the overall DCP accuracy. A gradient along the R-String2 can be neglected, as R-String2 has relaxed accuracy requirements.
Besides the wanted unit resistor elements layout related additional resistances are unavoidable which decrease the overall DCP performance. Contact resistances RC and wiring resistances RW are the dominating error sources for the DNL performance of the discussed DCP topologies.
Fig. 3 shows the modeled yield function of the 12 bit DCP (65nm) as a function of the unit resistor tolerances of R-String1 and R-String2. The black square in the plots shows the indirectly measured yield point based on estimations of the standard deviations of the measured unit resistors of both RStrings. This result shows the optimization potential of the DCP in terms of area efficiency, as the unit resistor tolerances of both R-Strings could be smaller without degrading the yield performance of 100%, leading to a smaller physical size of the DCP layout area. A safety margin should be defined to take other technology related variations into account.
Figure 3: Yield as function of sR-String1 and sR-String2
III. IP DESIGN PLATFORM
The benefits of Executable Design Descriptions have been successfully demonstrated for different design examples recently . Excellent results were achieved with respect to the increased engineering efficiency and reuse capability. A language based design entry for analog circuit design, in addition to the established graphical one, offers the required flexibility to realize complex full custom designs, especially for the portable and configurable DCP architecture considered in this paper. Main idea is to pay special attention to the IP engineering process itself instead of looking mainly to the result of it. Design parameters, PDK selections and even design frameworks can be exchanged easily during the IP engineering process. Fig. 4 shows the professional development platform 1Stone® (IPGEN) as a valuable extension to a Mentor or Cadence based design framework. The generic engineering model (GEM) design approach can be followed without exiting or shortening the already qualified design flows and by supporting the original PDKs from the process vendors. The graphical design entry stays available. A compiling process allows to execute the structured design descriptions and to compile the result into the database of the design framework. This includes schematics, layout and testbenches. The GEM design flow supports decoupling of design and process related data and is therefore an enabler to process portability.
Figure 4: Design Flow Extension that enables IP Retargeting and Design Porting
1Stone® allows to organize engineering steps for hierarchical designs in an efficient, reliable manner and enables to execute it automatically. The design stays a full custom design since no common circuit synthesis takes places. Each action has to be defined, like in handcrafted design. But it can be done independently from a process technology and with a remaining high variability of the design parameters for an unlimited number of circuit hierarchies. In addition new algorithm based approaches can be addressed to optimize yield and reliability of the circuit design.
IV. MEASUREMENT RESULTS 
Three different IP compilations into two different process technologies have been fabricated and measured (Table 1). 180nm CMOS is the latest process-node for automotive applications.
The measurement results indicate excellent DCP-IP portability capabilities proven by excellent linearity results at block level in presence of changing process environment conditions. The tolerances s of the unit resistors of R-String1 and R-String2 have been estimated out of the measured node voltages, assuming a constant current through R-String1 and R-String2. Comparing the DCP areas shows a factor of 4 between 12 bit and 14 bit and a factor of approx. 8 between 12 bit/65 nm and 12 bit/180 nm, which is in line with technology scaling principles. The measured standard deviation of R-String2 for the 14bit DAC case is about 3%. This is not critical in this architecture for related INL and DNL values. Comparing the 12 bit DAC accuracy in terms of INL and DNL between 65 nm and 180 nm shows an accuracy improvement after down-scaling, taking the LSB size into account.
Table 1: DCP performance summary
IC technology process scaling introduces increasing non-idealities. Manufacturing parameter variation is one of these. This work has shown that predictable parameter variations can be utilized even to improve quality and reliability of analog circuit design beyond known limits. A parameter variation aware 14 bit 1V Digital Controlled Potentiometer has been designed and fabricated in a 65nm digital standard CMOS process. It reaches 1LSB INL without using error correction. The implemented behavioral model library allows balancing the tradeoff between DCP yield and DCP layout area for a given performance specification taking the relevant statistical and systematic error sources into account. Regularity has been found as one of the keys for accurate and reliable analog circuit design in nano-scale process technologies. The implemented executable design description (GEMapproach) ensures the management of the whole design process and is able to create all necessary design views almost automatically. Executable Design Descriptions provide a significant enhancement of the design efficiency. Coming out of the GEM-descriptions, behavioral models are tailored to the actual realization. Reliability is ensured by providing a set of testbench-views for verification and optimization. Particular features of this design approach are the compatibility to given design flows, tools, and PDK’s, and the remaining high degree of flexibility: Design parameters persist variable and designs stay portable between different PDK’s and technology processes.
The authors thank the Nokia Research Center for certain contributions to this work.
 R. Wittmann, W. Schardein, B. J. Hosticka, G. Burbach, J. Arndt, "Trimless high precision ratioed resistors in D/A- and A/D converters," IEEE JSSC, vol. 30, no. 8, pp. 935-939, Aug. 1995
 R. Wittmann, D. Bierbaum, W. Schardein, E. Matei, "A parameterizable and process retargetable high speed DAC for digital radio applications", 12th Annual IEEE 1999 International ASIC/SOC Conference, Washington, Sept. 1999
 R. Wittmann, N. Nandra, J. Kunkel, M. Vanzi, J. Franca, H.-J. Wassener, Ch. Münker, "Life begins at 65 – Unless you are mixed-signal?", Proceedings DATE 07, Nice, 16-20 April 2007, pp. 936-941, IEEE Computer Society, ISBN 978-3-9810801-2-4
 M. Kosakowski, R. Wittmann, W. Schardein, “Statistical averaging based linearity optimization for resistor string DAC architectures in nanoscale processes”, 21st Annual IEEE International SOC Conference, Newport Beach, Sept. 2008
 M. Kosakowski, R. Wittmann, W. Schardein, H.-J. Jentschel, “Yield prediction and optimization to gain accurate devices for analog design in nonideal nanoscale processes“, International Workshop on Symbolic and Numerical Methods, SM²ACD '08, Erfurt, Oct. 2008