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Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
Filter banks, part 1: Principles and design techniques
By Chris Eddington, Synopsys
dspdesignline.com (January 15, 2009)
This two-part series introduces filter banks and shows how to implement them with high-level synthesis tools. Part 1 covers the principles of filter bank design.
Filter banks are part of a group of signal processing techniques that decompose signals into frequency subbands. This decomposition is useful because frequency domain processing (also called subband processing) has advantages over time domain processing. Due to their computational requirements, filter banks are typically implemented in FPGAs or ASICs.
The implementation process involves two main phases: architectural exploration and logic design. With traditional approaches, both phases are time-consuming and error-prone. High level synthesis (HLS) tools, which have been available for some time, help simplify these design issues. Most of these tools, however, have difficulty addressing the multi-rate behavior and intrinsic parallelism found in filter bank processing.
In this two-part article, we will show how a new generation of HLS tools overcomes this limitation by supporting multi-rate parallelism at multiple levels in the design flow. We will show how these enable rapid architectural exploration and implementation. We will illustrate multi-rate architectural transformation and optimizations, and show how they can reduce design and verification effort, thereby increasing the reliability of the entire design process. Part 1 provides a brief overview on the main filter bank concepts and a basic HLS design flow. Part 2 provides more details on HLS implementation.
dspdesignline.com (January 15, 2009)
This two-part series introduces filter banks and shows how to implement them with high-level synthesis tools. Part 1 covers the principles of filter bank design.
Filter banks are part of a group of signal processing techniques that decompose signals into frequency subbands. This decomposition is useful because frequency domain processing (also called subband processing) has advantages over time domain processing. Due to their computational requirements, filter banks are typically implemented in FPGAs or ASICs.
The implementation process involves two main phases: architectural exploration and logic design. With traditional approaches, both phases are time-consuming and error-prone. High level synthesis (HLS) tools, which have been available for some time, help simplify these design issues. Most of these tools, however, have difficulty addressing the multi-rate behavior and intrinsic parallelism found in filter bank processing.
In this two-part article, we will show how a new generation of HLS tools overcomes this limitation by supporting multi-rate parallelism at multiple levels in the design flow. We will show how these enable rapid architectural exploration and implementation. We will illustrate multi-rate architectural transformation and optimizations, and show how they can reduce design and verification effort, thereby increasing the reliability of the entire design process. Part 1 provides a brief overview on the main filter bank concepts and a basic HLS design flow. Part 2 provides more details on HLS implementation.
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