English
Li-Ion Battery Charger - ±1% Accuracy (4.2V) / Up to 1500mA Fast Charge Silterra 0.18 μm
SAS--SATA: What You Need to Know for 6 Gb/s and Beyond
Chris Cicchetti, Finisar
commsdesign.com (Jan 25, 2009)
The introduction of 6 Gb/s SAS-2 and SATA Gen-3 promises new levels of performance for networks. At these higher speeds, however, signal integrity becomes a significantly more important design concern for equipment designers and network engineers than it was at 3 Gb/s as tolerances drop to the point where test equipment can adversely affect signal integrity. For example, a test setup that was already at the performance edge for 3 Gb/s will cause undesirable and misleading failures at 6 Gb/s.
Apart from strictly adhering to each standard's specifications, the key behind successful SAS/SATA product development and network debugging will be an understanding of the tighter tolerances at 6 Gb/s and the simple steps that one can take to minimize the impact of test equipment on the device under test. By understanding how attenuation and jitter impact signal integrity, developers and systems engineers can adjust test setups to minimize their impact during testing.
commsdesign.com (Jan 25, 2009)
The introduction of 6 Gb/s SAS-2 and SATA Gen-3 promises new levels of performance for networks. At these higher speeds, however, signal integrity becomes a significantly more important design concern for equipment designers and network engineers than it was at 3 Gb/s as tolerances drop to the point where test equipment can adversely affect signal integrity. For example, a test setup that was already at the performance edge for 3 Gb/s will cause undesirable and misleading failures at 6 Gb/s.
Apart from strictly adhering to each standard's specifications, the key behind successful SAS/SATA product development and network debugging will be an understanding of the tighter tolerances at 6 Gb/s and the simple steps that one can take to minimize the impact of test equipment on the device under test. By understanding how attenuation and jitter impact signal integrity, developers and systems engineers can adjust test setups to minimize their impact during testing.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- When Traceability Catches What Verification Does Not
- Implementing C model integration using DPI in SystemVerilog
- Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
- Lossless Compression Efficiency of JPEG-LS, PNG, QOI and JPEG2000: A Comparative Study
- Four ways to build a CAD flow: In-house design to custom-EDA tool