English
PRODUCT HOW-TO: Hardware IP design reuse made easy with Altium's Innovation Station
By Phil Loughhead, Altium Ltd.
Embedded.com (01/30/09, 09:43:00 PM EST)
The ability to reuse existing sections of designs is like the quest for the holy grail in our design team - something we value highly and dream of finding, but have yet to discover. And if you were to push me to take a position, I used to doubt it would ever be found.
So I'd have to say that I was skeptical when I read statements about design reuse in Altium Designer - "I'll believe that when I see it" were my exact words.
Everyone in the team was already practicing design re-use, we were copying and pasting sections of existing designs " like standard comms or power supply sub-circuits " into our current projects.
But there was no integrity in the copied design, because any number of mistakes could be made during the copy/paste process, and the engineer could and would modify the circuit to suit their idea of a good circuit. That meant it had to be subject to the standard review and triple-check sign-off process.
Embedded.com (01/30/09, 09:43:00 PM EST)
The ability to reuse existing sections of designs is like the quest for the holy grail in our design team - something we value highly and dream of finding, but have yet to discover. And if you were to push me to take a position, I used to doubt it would ever be found.
So I'd have to say that I was skeptical when I read statements about design reuse in Altium Designer - "I'll believe that when I see it" were my exact words.
Everyone in the team was already practicing design re-use, we were copying and pasting sections of existing designs " like standard comms or power supply sub-circuits " into our current projects.
But there was no integrity in the copied design, because any number of mistakes could be made during the copy/paste process, and the engineer could and would modify the circuit to suit their idea of a good circuit. That meant it had to be subject to the standard review and triple-check sign-off process.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- PRODUCT HOW-TO: Debugging hardware designs with an FPGA-based emulation tool
- PRODUCT HOW-TO: Taking the delay out of your multicore design's intra-chip interconnections
- PRODUCT HOW-TO: Use ARM DBX hardware extensions to accelerate Java in space-constrained embedded apps
- FPGA constraints for the modern world: Product how-to
- Product How-to: Fully utilize TSMC’s 28HPC process
New Articles
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
- Embracing a More Secure Era with TLS 1.3
- New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI
- Maximizing ESD protection for automotive Ethernet applications