This article shows how a CPLD can replace a digital-to-analog converter, allowing it to drive an audio speaker or control things like LED intensity, motor speed, and servo position.
By Rafael Camarota, Altera
industrialcontroldesignline (February 24, 2009)
Although the Altera MAX IIZ CPLD is a digital programmable logic device, it is versatile enough to control analog systems. This article shows how MAX IIZ CPLDs – alone or with a few passive components – can replace digital-to-analog converters, thereby allowing them to drive devices like audio speakers or control things like LED intensity, motor speed, and servo position. The article also explains pulse-width modulator (PWM) operation, as well as describing the efficient implementation and use of PWMs in a MAX IIZ CPLD.
A pulse-width modulator (PWM) is a common way of generating analog outputs from a digital component. A PWM replaces a digital-to-analog converter (DAC) that generates analog voltage or current proportional to the digital input. As the name implies, a PWM generates a series of constant voltage or current digital pulses with pulse widths or duty cycles that are proportional to the intended analog strength. The series of modulated pulses can be converted to an analog voltage with a low-pass filter, but this is usually not necessary.
Fig 1 shows a typical analog signal and its corresponding digital PWM representation. In general, an analog signal has maximum amplitude, minimum amplitude, and many levels in between. In contrast, the PWM only has two levels: maximum and minimum.
1. Analog signal and equivalent pulse-width modulation.
(Click this image to view a larger, more detailed version)
To convert from analog to digital, the analog signal first is sampled at a carrier frequency. For a given sample period, the area under the analog signal equals the area under the PWM pulse. The key principle behind the PWM is that a short pulse at maximum amplitude has the energy equivalent to a continuous analog signal at a lower amplitude. This simple equation determines the required sample frequency for a PWM circuit: FSAMPLE = 2 × FRANGE
...where FSAMPLE is the rate at which the analog signal is divided into digital packets, and FRANGE is maximum frequency of the analog signal to be reproduced by the PWM. In the case of audio, for example, this may be 4 KHz for a phone or 20 KHz for an MP3 player. The "2" in the equation comes from the Nyquist frequency, which is the accepted oversampling rate required to reproduce an analog signal from digital samples.
The next step is to generate a clock to drive the PWM granularity. The following equation determines the PWM frequency: FPWM = 2 × FRANGE × R
...where FPWM is the clock frequency driving the PWM block, and R is the resolution. The resolution is typically a multiple of 2N (where N = number of bits in the digital data stream words), however with the proposed MAX IIZ PWM, any resolution is possible.
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