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How to detect solder joint faults in operating FPGAs in real time
Without early detection, electrical anomalies caused by solder joint faults can result in the catastrophic failure of mission-critical equipment.
By Phillip Davies, Ridgetop Group
pldesignline.com (March 04, 2009)
The problem: Solder joint faults in FPGAs
Solder joint faults can be described with a single word – pernicious. Solder joints connect the BGA package, containing an FPGA (Field Programmable Gate Array) core, to the PCB (Printed Circuit Board). Without early detection, electrical anomalies caused by solder joint faults can result in the catastrophic failure of mission-critical equipment.
In order to prevent this, Ridgetop Group designed the Sentinel SJ BIST EPU (Solder Joint Built-In Self-Test Electronic Prognostic Unit). Part of a line of electronic prognostic solutions, SJ BIST provides real-time detection of solder joint faults in any operating FPGA for military, aerospace, and automotive applications.
Solder joint faults can occur with FPGAs found in all types of commercial and defense products. When embedded in BGA (ball grid array) packages, FPGAs become susceptible to failure from solder joint faults. The causes of solder joint faults cannot be isolated, early detection is difficult, and the intermittent failures escalate in severity until devices are rendered unreliable or inoperable. But, as so often seems to be the case, the problem is also the solution...
Stress-related faults
In operational devices, the primary contributors to solder joint faults are thermo-mechanical and shock stresses. Whether from vibration, torque forces, thermal cycling, material expansion, or environmental stresses, the inevitable result is mechanical failure from cumulative damage. At the solder joint level, the damage is seen as a crack at the package/PCB boundary, although there are other possible points of failure in the solder joint network.
Statistical degradation modeling is the current method for predicting solder joint faults in programmed, operating FPGAs. However, since statistics vary and work best at trending large populations, statistical degradation modeling is a stop-gap solution, at best. With SJ BIST, Ridgetop Group provides a true tool for direct, in-situ measurement of prognostic indicators of faults in operating solder joint networks.
By Phillip Davies, Ridgetop Group
pldesignline.com (March 04, 2009)
The problem: Solder joint faults in FPGAs
Solder joint faults can be described with a single word – pernicious. Solder joints connect the BGA package, containing an FPGA (Field Programmable Gate Array) core, to the PCB (Printed Circuit Board). Without early detection, electrical anomalies caused by solder joint faults can result in the catastrophic failure of mission-critical equipment.
In order to prevent this, Ridgetop Group designed the Sentinel SJ BIST EPU (Solder Joint Built-In Self-Test Electronic Prognostic Unit). Part of a line of electronic prognostic solutions, SJ BIST provides real-time detection of solder joint faults in any operating FPGA for military, aerospace, and automotive applications.
Solder joint faults can occur with FPGAs found in all types of commercial and defense products. When embedded in BGA (ball grid array) packages, FPGAs become susceptible to failure from solder joint faults. The causes of solder joint faults cannot be isolated, early detection is difficult, and the intermittent failures escalate in severity until devices are rendered unreliable or inoperable. But, as so often seems to be the case, the problem is also the solution...
Stress-related faults
In operational devices, the primary contributors to solder joint faults are thermo-mechanical and shock stresses. Whether from vibration, torque forces, thermal cycling, material expansion, or environmental stresses, the inevitable result is mechanical failure from cumulative damage. At the solder joint level, the damage is seen as a crack at the package/PCB boundary, although there are other possible points of failure in the solder joint network.
Statistical degradation modeling is the current method for predicting solder joint faults in programmed, operating FPGAs. However, since statistics vary and work best at trending large populations, statistical degradation modeling is a stop-gap solution, at best. With SJ BIST, Ridgetop Group provides a true tool for direct, in-situ measurement of prognostic indicators of faults in operating solder joint networks.
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