English
Using software verification techniques in non-safety critical embedded software designs
By Paul Humphreys, LDRA Ltd.
Embedded.com (03/23/09, 09:00:00 AM EDT)
The aerospace and automotive industries are well known for the rigorous software quality standards to which they must adhere, but developers of non-safety critical systems can also benefit from the type of standards employed within these industries. In addition to producing reliable software, development costs can be contained and requirements met more easily by observing a software quality process.
Software development often proves far more expensive than expected; bugs discovered late in the development cycle send costs soaring and risk the integrity and safety of a system, especially if the software has been deployed. Obviously, careful planning, organization and a team with the correct skills all help. However, it is verification and validation (V&V) that identify when and how the development process drifted from what was intended or required by the user.
What's the difference between verification and validation? Validation focuses on producing the right software system while verification ensures the software is built the right way. V&V should be evident at each stage of development and conducted with reference to the outputs from previous stages.
Verification is at the hub of a quality process, evaluating whether or not a product, service, or system complies with a regulation, specification, or conditions imposed at the start of a development phase.
Embedded.com (03/23/09, 09:00:00 AM EDT)
The aerospace and automotive industries are well known for the rigorous software quality standards to which they must adhere, but developers of non-safety critical systems can also benefit from the type of standards employed within these industries. In addition to producing reliable software, development costs can be contained and requirements met more easily by observing a software quality process.
Software development often proves far more expensive than expected; bugs discovered late in the development cycle send costs soaring and risk the integrity and safety of a system, especially if the software has been deployed. Obviously, careful planning, organization and a team with the correct skills all help. However, it is verification and validation (V&V) that identify when and how the development process drifted from what was intended or required by the user.
What's the difference between verification and validation? Validation focuses on producing the right software system while verification ensures the software is built the right way. V&V should be evident at each stage of development and conducted with reference to the outputs from previous stages.
Verification is at the hub of a quality process, evaluating whether or not a product, service, or system complies with a regulation, specification, or conditions imposed at the start of a development phase.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Platform Software Verification Framework Solution for Safety Critical Systems
- Platform Software Verification Approaches For Safety Critical Systems
- Processor-In-Loop Simulation: Embedded Software Verification & Validation In Model Based Development
- Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs
- Dealing with automotive software complexity with virtual prototyping - Part 3: Embedded software testing
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UVM RAL Model: Usage and Application
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)