An important weapon in the verification arsenal is formal verification. Rajeev Ranjan, Jasper Design Automation EE Times (07/13/2009 12:00 AM EDT)
As designers approach 45 nm, the difference between ASICs and SoCs really blurs and, essentially, all chips become SoCs. At the same time, platform-based design, with the use and reuse of internal and external IP blocks, is playing a bigger and bigger role, because nobody is going to build a 50-M gate chip from scratch. In this changing environment, formal verification should be integral to these flows, but several common misconceptions may slow adoption of this critical technology.
What is indisputable though is that all today's conventional verification tools are proving insufficient as we head toward 45-nm designs; and building faster and larger compute farms and utilizing specialized hardware is not the answer. New methodologies and technology are needed, and quickly, to address the challenge.
An important weapon in the verification arsenal is formal verification. Once the province of experts with very specialized knowledge, over time the difficult parts have been pushed under the hood and formal verification has attracted a broader audience. Over the past five years, formal verification was deployed first by experts on the verification team, then by the entire verification team and lately it has been spreading to the designers themselves.
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