Jerry Frenkil, Sequence Design EE Times (07/13/2009 12:00 AM EDT)
The issue of verification has never been larger. Today, functional verification is at least as big a task as design and, in many cases, much larger. This has been the case for awhile now and the situation doesn't appear to be changing any time soon. If anything, verification is becoming an even larger and more difficult task.
It isn't hard to see why. More transistors and larger die sizes result in greater complexity. It is common today to see single chips with multiple CPUs and multiple memory systems, a DSP, and various interfaces such as USB, 802.11, and Bluetooth not to mention a healthy smattering of analog functions. And don't forget power management.
Accompanying all of the increased complexity is increased power consumption although, thanks to designer creativity, power consumption has not increased as rapidly as functional complexity. Various types of power reduction techniques have been employed to keep power concerns from derailing functional aspirations. After all, what good is a shiny new phone with video capabilities if the battery life is measured in minutes instead of hours or days?
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