The ever critical communication bus structuresBy Santanu Dutta, Jens Rennert, Tiehan Lv, Jiang Xu, Shengqi Yang, and Wayne WolfEmbedded.com (08/18/09, 05:35:00 PM EDT)
Multimedia SoCs frequently house multiple processor cores that share the task of running the operating system and controlling the critical and noncritical on-chip functional-unit resources.
In this context, an efficient bus architecture and arbitration (for reducing contention) play important roles in maximizing system performance. Besides, for many applications, the performance of multiprocessor systems relies heavily on an efficient communication between the processors and a balanced load distribution (of computing tasks) among them.
With multiple CPUs and a plethora of functional units, on-chip communication poses a critical design problem that is often solved using multilevel hierarchical busses connected via local bridges, the bridges primarily serving as protocol converters between different bus systems and/or connectors between busses with different speeds (e.g., high-speed processor bus and low-speed peripheral bus).
CoreConnect, for example, has three levels of hierarchy: processor local bus (PLB), on-chip peripheral bus (OPB), and device control register (DCR). PLB provides a high-performance and low-latency processor bus with separate read and write transactions, whereas OPB provides low speed with separate read and write data busses to reduce bottlenecks caused by slow I/O devices; the daisy-chained DCR offers a relatively low-speed datapath for communicating status and configuration information.
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