High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems
By Tsun-Kit Chin, National Semiconductor Corp.
pldesignline.com (November 18, 2009)
Television and cinema have entered the digital age. Video pictures are used to transport at standard definition rate (270 Mb/s), upgraded to high definition rate (1.485 Gb/s), and are now migrating to 3 Gb/s. The migration to higher speeds enables higher resolution images for entertainment, but it also presents challenges to hardware engineers and physical layout designers. Many video systems are implemented with feature-rich FPGA and multi-rate SDI integrated circuits that support high performance professional video transport over long distances. FPGAs demand high density routing with fine trace width while high-speed analog SDI routing demands impedance matching and signal fidelity. This paper outlines the layout challenges facing hardware engineers and provides recommendations for dealing with these challenges.
|E-mail This Article||Printer-Friendly Page|
Search Silicon IP
- Safeguarding the Arm Ecosystem with PSA Certified PUF-based Crypto Coprocessor
- Mastering Key Technologies to Realize the Dream - M31 IP Integration Services
- Create high-performance SoCs using network-on-chip IP
- IoT Security: Exploring Risks and Countermeasures Across Industries
- How Efinix is Conquering the Hurdle of Hardware Acceleration for Devices at the Edge