Altera courts ASIC designers with block-based Stratix PLD
Altera courts ASIC designers with block-based Stratix PLD
By Anthony Cataldo, EE Times
February 11, 2002 (6:59 p.m. EST)
SAN FRANCISCO Looking to snatch the lead from archrival Xilinx Inc., Altera Corp. has taken the veil off a programmable-logic architecture that it hopes will dazzle ASIC designers and reclaim turf lost to Xilinx's Virtex product.
Built from the ground up in just 13 months, the Stratix architecture aims to ratchet up logic density and speed while giving designers ways to take advantage of more modular, reusable intellectual-property blocks and tighter memory configurations.
Stratix is being positioned as a worthy substitute for system-on-chip designs based on an ASIC methodology. In fact, Altera's engineers made heavy use of simulations based on existing ASIC designs as they developed Stratix.
The completion of Stratix comes none too soon for Altera, whose current Apex line of products has lost key design wins to Xilinx's Virtex in recent years, according to analysts.
"The Virtex product line has proved to be a solid product that is good at integrating IP at a rapid rate," said Bryan Lewis, an analyst with Gartner Dataquest. "And I had heard that the Virtex tools were superior and that is what got designers interested."
With Stratix, Altera claims it will overcome earlier deficiencies and ultimately overtake its biggest rival. John Daane, president and chief executive officer of Altera, said he expects Stratix-based products to generate $150 million in revenue next year.
| Dedicated receiver and transmitter interfaces are part of Altera's Stratix PLD architecture. |
"If he can pull that off, that would be a very quick ramp," Lewis said. "He's betting that it is one of the best if not the best ramps that Altera will ever have by making th at statement."
There are few aspects of the PLD architecture that Altera did not tinker with when creating Stratix. The core logic elements are still based on a four-input lookup table, but the normally tightly coupled registers have been let loose to do more work.
Stratix also gives designers more routing resources to play with. Perhaps more important, the interconnect is uniform across the die, and with the help of Altera's latest tools designers can freeze functional blocks and reposition them on the design or use them for another design without having to resynthesize.
PLD designers today are often forced to change the aspect ratios of their IP blocks to meet their timing requirements when changes are introduced. Altera's DirectDrive feature ensures that the signals propagate at the same rate no matter where the block is placed on the chip or how many logic resources are being used in nearby regions. Whereas before multiple sources drove a route l ine, there's now a single buffer to keep the loading consistent.
"No matter where you are on the chip it always has the same access to the logic elements, so it's friendly for block-based designs," said Daane. "Engineers are already used to this style of design, but now we're doing it for a PLD medium."
Besides easing the design process, Altera claims Stratix will provide an average of 40 percent better performance than its current-generation devices, thanks largely to a fourfold increase in routing resources. Even higher performance is expected for designs that take advantage of special features of the company's Quartus 2 software.
There are three types of interconnect for making connections to a block or between blocks or for long-haul busing which vary by length and drive strength. By varying the width and spacing of the wires, Altera said, it was able to reduce the amount of area the wires consume on the chip.
The cumulative die area reduction for Stratix o ver its prior architecture, including a process shrink, is 50 percent, allowing the company to pack in higher memory, dedicated DSP blocks and other features. The area reduction should also help increase wafer yield, reducing manufacturing costs, since interconnect accounts for much of the bulk in programmable logic.
Altera was also able to attain better logic efficiency by coaxing the registers within basic logic elements to do double duty. A logic element (LE) comprises a lookup table and a register, and the two are normally treated as one unit. In this case, Altera partially disassociated the two building blocks, enabling the LUT to drive one output while the register drives another output.
That "register packing" feature essentially means the registers and LUTs can be used for separate functions, reducing by 15 percent the number of LEs needed for a typical function, Altera claims.
To address SoC designers' insatiable appetite for memory, Stratix gives designers a choice of three types of on-chip memory, with differing bandwidth and granularity characteristics. For the highest-density device, 10 Mbits are available.
The number of bits for each memory block is inversely proportional to the number of ports per 1,000 bits. For example, applications that need higher bandwidth could use the 512-bit-per-block option, which supports 32 ports for every 1,000 bits. "There are applications where people wanted to use shallow FIFOs that were eight or 16 words deep, but it was 4 kbits that limited them. For those scenarios, we could address the buffering requirements with the smaller blocks," said Steve Mensor, senior director of product marketing at Altera.
Another option offers 4 kbits at each block, with eight ports for every 1,000 bits. The densest memory option is the MegaRAM, which offers 512 kbits per block but only one port for every 4,000 bits. Touted as an industry first, MegaRAM is a nod to those who are stuffing their designs with more memory to eke out higher perform ance.
"People just want more bits, and it's hard to do with 4-kbit blocks. The MegaRAMs are efficient from a bit per die-area metric," Mensor said.
Among the markets Altera would like to bust open are those that make heavy use of digital signal processing. Instead of providing basic adders, Stratix embeds up to 28 multiply-accumulate units that run at 250 MHz.
The DSP blocks could help Altera gain more design wins in 3G basestations, which often rely on programmable logic devices to do chip-rate processing in parallel. This is a coveted area for vendors of high-end PLDs and one in which Xilinx has had an edge, said Will Strauss, president of Forward Concepts (Tempe, Ariz.).
"Altera has a greater depth of DSP algorithms, cores and software than Xilinx, but Xilinx has a bigger share of the market because they were first," Strauss said.
Stratix can plug into a raft of I/O schemes and external memory devices with different interfaces. Its I/O roster includes differential and single-ended I/Os like LVDS, HSTL and PCI and high-speed protocols such as 10-Gigabit Ethernet and POS-PHY 4. Stratix supports DDR DRAM and SRAM, QDR and QDR-2 SRAM, ZBT SRAM and DDR FCRAM.
Similar to what Xilinx did for Virtex, Altera will bring termination resistors on-chip as a way to simplify board design, improve signal integrity and reduce cost. But Altera's approach includes differential termination resistors. As for clock management, Stratix can accommodate as many as 12 phase-locked loop circuits.
For now, Altera isn't saying how Stratix matches up with competing products. Xilinx is expected to introduce a Virtex device soon that embeds a PowerPC into the middle of its FPGA fabric to enable 3.125-Gbit/second serial links. Altera's current Mercury family of transceivers can run at 1.25 Gbits/s. Altera provides the ARM9 hard core and its own Nios microcontroller as a soft core for its existing products. Mensor said Stratix is suited for embedding f uture IP.
The first 0.13-micron device, with 25,660 logic elements, is set to debut in June, and Altera plans to roll out seven more devices by 2003. It hopes to churn out Stratix-based products at a faster clip with the help of a new simulator, which draws from a database of real ASIC designs gleaned from customers.
"The way we used to do an architecture is to look at what made sense from a marketing perspective, put it on a white board and build a compiler. That took six to nine months," Mensor said. "With this we were able to build multiple architectures within a single week, and that includes analysis of the die area."
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