edadesignline.com (January 07, 2010)
As more complex, mixed signal System on Chip (SoC) designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed signal verification presents a unique challenge as the analog portion of the design requires highly accurate, and time consuming, analog simulation (Spice for example).
Furthermore, without a digital representation of the analog design, full digital regression simulations are not possible for the SoC. This is insufficient for verifying connectivity and basic functionality of the integrated SoC at the system level. Intrinsix recently evaluated the Cadence Design Systems' Real Number Modeling (RNM) methodology as a possible solution for achieving efficient mixed signal verification.
Intrinsix is a leading supplier of sigma-delta data converter IP. Many of our customers are using Sigma-Delta Modulator (SDM) technology to develop sensors for automotive, consumer and aerospace applications. All of these designs require similar signal processing.
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