System-on-chip design teams face several daunting tasks in optimizing their next-generation products. Since SoC designs can consist of multiple intellectual property (IP) blocks, and silicon geometries continue to shrink and designs migrate to lower geometries, approaches are needed to ensure that IP can be transferred from one process geometry to the next, and that IP blocks are efficient and optimized for reuse. Industry estimates indicate that 60 percent to 70 percent of IP expenditure goes to porting to a new process technology, not in creating new intellectual property.
IP developers have realized that they must have a reuse strategy when developing new intellectual property. To effectively implement IP reuse, developers must consider design efficiency, tool efficiency and timely silicon prototyping.
The IP reuse strategy depends upon the initial development approaches of the intellectual property. So design efficiency and the reuse of IP are the first considerations of the developer. The goal is to efficiently design a core that is independent of certain process-geometry tolerances.
To achieve design efficiency, developers often take a modular, top-down approach. This allows individual modules to be more easily ported to a new process because the developer looks at the architecture and attempts to design cores and blocks that are less dependent on process tolerances. With this approach, it is possible to move from one geometry to the next without dramatically changing the design architecture. The design framework remains almost the same, requiring only fine-tuning at the end of the development cycle.
Because reuse is not a 100 percent automated process, another challenge facing developers is tool efficiency. This becomes extremely important as designs move to the smaller geometries. As geometries shrink to 0.18 micron and below, problems surface that affect analog/digi tal functions, such as signal integrity and crosstalk. Certain tools can address the problems of noise, IR drop, power estimation and other tool-related issues. If the right tools are not implemented to handle these concerns in certain processes, then the optimization and functionality of IP for smaller geometries is drastically limited. These problems can result in reduced yield and/or even chip failures. EDA tools that help to ensure working silicon are important.
A third challenge for IP developers is the need to quickly fabricate silicon prototypes to verify a design in silicon. Until a design is implemented in silicon, the developer is uncertain about his design functionality. Simulations with design tools are necessary first steps, but silicon implementation is the only way to verify final functionality.
Timely silicon prototyping is still an unresolved issue at vertically integrated ASIC providers and integrated device manufacturers (IDMs), since their first priority is producing proven designs for customers, not fabricating test chips. Because of this internal conflict, IP developers working for these companies find themselves waiting in the fab queue several months before seeing a design in silicon. This causes delays of three to five months in the design cycle, slowing time-to-market and increasing development costs.
To overcome this time-to-market dilemma, Taiwan Semiconductor Manufacturing Company (TSMC) has initiated a fast prototyping program called CyberShuttle. CyberShuttle allows IP developers to share a common mask that contains up to 16 different designs. Shuttles are run monthly on a dependable schedule, so developers don't have to wait for months to see their design implemented in silicon. Instead of waiting three to five months or sometimes longer at each spin to see silicon, IP developers have samples in six to eight weeks. This can save at least four to six months, for each IP, on a normal development cycle that requires two respins. There is no charge fo r the CyberShuttle service for TSMC's IP Alliance partners.
Signia Technologies in December 2000 successfully demonstrated the world's first 0.25-micron RFCMOS 2.4-GHz Bluetooth radio transceiver IC, and rapidly developed a Bluetooth baseband controller IC employing TSMC's process. Signia's Ulysses SBT-5010 was the first Bluetooth transceiver demonstrated in TSMC's commercially available, volume 0.25-micron RFCMOS process. RFCMOS is a high-volume CMOS process for RF devices such as high-Q thick-metal spiral inductors, metal-injection molding (MIM) capacitors, triple-well isolated NMOS transistors, varactor diodes and high sheet-resistance polysilicon resistors.
The SBT5010 transceiver contains complete transmit and receive functions including a fully integrated synthesizer. As such, this is a true system-on-chip design that eliminates external filters and inductors, leading to a smaller footprint and a lower component count.
The controller contains the complete Bluetooth core functionality, including hardware-accelerated encryption, decryption and authentication. The chip contains a microprocessor and on-board static RAM for easy implementation into notebook PCs, PDAs and Internet appliances. It provides an innovative host interface that can support a wide variety of connections such as PCMCIA, parallel/printer ports, and PCI interfaces, as well as standard interfaces such as USB, UART and I2C. This IC was developed using TSMC's CyberShuttle for rapid development as well as IP for peripheral functions.
Promoting IP reuse
Leveraging third-party alliances provides industrywide solutions to the challenges of IP reuse and porting to next-generation technologies. It creates an environment that promotes and facilitates silicon IP reuse by making it easier to acquire and integrate IP blocks. Alliances and partnerships that provide third-party, silicon-verified IP cores, libraries, best-of-class EDA tools, accurate simulation, validation and verification, al ong with rapid prototyping lower the barriers for SoC designers to use and reuse IPs.
TSMC's Design Service Alliance brings together third-party IP providers, library vendors, EDA tool vendors and chip implementation services. This alliance promotes an environment for each category to come together under one umbrella with one goal-to help make the mutual customer successful. The alliance also allows partners to address industrywide issues such as IP reuse in a more collaborative environment. For instance, by providing optimized libraries in a certain process, the path for the IP providers to optimize their IP in the same process will be much shorter.
Adherence to standards in development is also a major factor in IP reuse. Recognizing this need, the Virtual Socket Interface Alliance (VSIA) was formed so that representatives from all segments of the SoC industry could work together to solve potential roadblocks with the reuse of IP. They work to accelerate system-on-chip development by s pecifying open standards that facilitate the mix and match of IP blocks from multiple sources.
Technical standards allow designers to mix and match and test IP cores, and ease the migration path to lower geometries. To facilitate this mix and match, VSIA specifies open interface standards that allow IP blocks to fit quickly into virtual sockets, both at the functional level and the physical level. For example, VSIA's concept of firm virtual circuits promotes reuse at the physical level.
This approach from VSIA will allow IP developers to produce and maintain a uniform set of IP deliverables, rather than have to support numerous sets of deliverables required for the many unique customer design flows.
Additionally, VSIA endorses emerging standards from other groups that meet its technical requirements. Only when nothing else exists or is emerging, does VSIA develop new standards for the industry. It works with other organizations to minimize ov erlap and support complementary efforts. Also, one of the increasingly important issues of any SoC design is the testing methodology for these IP blocks. Design for Test (DFT) needs to be on the IP developer's mind in order to minimize the time required to debug a problematic SoC design. Being able to isolate each block and test individual components separately is an essential task that is begging to be addressed as the level of sophistication and number of IP blocks grow in any SoC design.
Shortening the turnaround time when reusing IP requires access to experienced design support and timely silicon prototyping. By providing IP developers with services that promote quick cycle time and overcome silicon prototyping barriers, design teams will be able to efficiently reuse IP.