Top-down design meets bottom-up IP
By Hammam Elabd, Architect, email@example.com, Vijayaraghavan Ranganathan, Architect, firstname.lastname@example.org, Suresh Dholakia, SVP Product & Technology, email@example.com, RealChip Communications, EE Times
March 26, 2001 (3:03 p.m. EST)
The traditional ASIC model has relied on megacells and hard macros, which were custom-crafted and highly tuned. As process technology evolved, however, the tools needed to help migrate these quickly to smaller process geometries were absent. As a result, system-on-chip (SoC) developers discovered that it takes too long to develop, characterize and deploy these cells and hard macros for smaller process geometries.
A number of ways are available to accelerate the migration of communications SoCs to smaller process geometries. To achieve a rapid design cycle and the migration, developers must take advantage of previous design efforts. This implies repeated use of architectural verification tools, RTL (register-transfer level), verification environment and bus functional models of previously designed subsystems (blocks) as well as commercially available intellectual-property (IP) components. It also favors a hybrid, top-down design methodo logy with a bottom-up approach for new block development.
A rapid design cycle and the migration to new processes also dictate using soft IP, SoC architecture that attempts to use available off-the-shelf, plug-and-play IP components, optimizing the interfaces between IP subsystems by using standard bus systems and optimal hardware and software partitioning. These requirements demand a fully developed infrastructure such as hardware-description-language (HDL) coding standards, documentation, deliverables and interface standards to achieve IP reuse. They also demand repository maintenance efforts, sharing source control, change control and configuration management strategies among various internal users.
Today, new building blocks like signal processors, phase-locked-loop blocks, I/O blocks and memory are available in soft form. These soft building blocks, for instance, can be fully characterized in 0.18-micron technology and rapidly retargeted to 0.15-micron technology.
Con fronting incompatibility
The incompatibility of process technology among different foundries has long been a problem for SoC developers needing to switch foundries. However, today foundries are doing their part in trying to keep process technology consistent to aid in retargeting. In addition, alliances such the WorldLogic program, through United Microelectronics Corp. (UMC; Taiwan), IBM Corp. (Armonk, N.Y.), and Infineon Technologies AG (Munich, Germany) are creating consistent advanced process technology among a number of foundries. Looking forward, this advanced process standard will ease the work of IC developers.
Shrinking silicon technology calls for a pragmatic methodology with the existing tools and necessitates the adoption of soft solutions. The design cycle and the migration to new processes such as the UMC and Taiwan Semiconductor Manufacturing Co. Ltd (TSMC ) submicro n processes take the most advantage of previous design efforts by reconfiguring reusable objects, such as RealityObject from RealChip Communications, soft IP, with no changes or re-engineering of the subblocks. Optimized interfaces between IP subsystems and a standard bus system as well as optimal hardware and software partitioning are key to a short platform-based SoC development cycle.
The MoNet System Platform forms the core of the platform on which software and hardware objects, known as RealityObjects, are created. These reusable, reconfigurable objects allow various SoC products to be generated quickly by configuring the platform. In practical implementation, RealityObjects are prepared for various technologies, and test chips were developed to verify the performance of various technologies before developers freeze the core for applications.
In this process the designer uses the following capability models: ad hoc reuse, IP awareness, design for reuse, collaborative design and bus iness-to-business IP collaboration.
In ad hoc reuse, designers use a consistent directory structure, common libraries and configuration management at the project team level. In IP awareness development, the entire execution is constantly updated on the changes to the IP, maintaining a strict version, configuration control and change management. The design for reuse practice includes strict coding style to reuse RTL, verification, testability and physical design as well.
The MoNet platform design addresses physical design problems such as slew, negative delay, supply voltage variation and temperature variation to account for the effects of deep submicron effects in silicon models.
Cell, driver models linked
To control the slew-interconnect model, a cell model and driver model are used. These models are interdependent and help in accurate timing analysis of deep-submicron implementation. Tackling negative delay requires accurate threshold modeling techniques t hat are unique functions of cell types, pins, voltage, temperature and process.
The effect of supply voltage variations on circuit delay must be predicted. The circuit must be simulated to compute currents drawn by the gates. Then, a power/ground network must be simulated to measure the voltages everywhere. Chip temperature is proportional to the power dissipation. Temperature is treated as a local variable for each cell making it variable over time.
Crosstalk occurs because of cross-coupling capacitance between interconnects. As a signal switches, the voltage waveform of neighboring nets may be affected. This was not a concern up to 0.5 micron. The foundation for a crosstalk solution is an integrated, incremental static timing analyzer that understands cross-talk together with an accurate builtin cross-coupling, resistive-capacitive time-constant extractor.
IR drop is due to voltage drop of the power and ground due to high current flowing through the power ground resistive n etwork. The IR drop becomes more of a problem for deep-submicron designs because of an increase in current due to more devices in a design and higher current through each device.
It's also caused by an increase in wire and contact/via resistance due to narrower wires and fewer contacts/vias, and it can be the result of a decrease of supply voltage to 1.5 volts or less.
IR drop can cause the chip to fail due to performance (a circuit running slower than specification), functionality (setup or hold violations) or unreliable operation (less noise margin). Normally, a what-if analysis by adding power connections or changing power mesh structure is performed to meet IR drop specification. Electromigration and inductance problems for high frequencies are other issues to be tackled before successful tapeout.
A designer completes memory characterization by selecting corner instances.Typical selections are based on the criteria, such as small, la rge, narrow and wide. The designer also must characterize the selected instances and build a lookup table or equations by fitting curves. Finally, the designer generates a timing mode and conducts on-chip memory IP characterization.
The MoNet System Platform is based on a fully developed platform infrastructure including HDL coding standards, documentation, deliverables and interface standards to achieve IP reuse. Also included are repository maintenance efforts, sharing among various internal users, source control, change control and configuration management strategies.