Design styles seem to change as fast in the electronics industry as in the notoriously fickle fashion business. Where once it was de rigueur to tailor a custom processor in-house, suddenly design reuse is the rage, and system-on-chip (SoC) mavens are rifling bargain-basement intellectual property (IP) libraries for last year's castoffs. Cost and time-to-market now reign supreme-getting a quick fit is the key to success.
But with target silicon shrinking each season, fitting last year's designs to this year's process has become a design challenge in itself. Retargeted circuit designs still must be custom-fitted to new processes for reuse to work. That means reverification and test at smaller geometries. The question becomes: is it worth it?
|The Tuxedo team at Verplex--from left, C. Andy Lin, Kuang-Chien Chen, |
C. Michael Chang--tackled the reuse problem at its root with a design system that simultaneously retargets and verifies IP.
"Whether the originator or the end user of the IP performs the verification, there is no escape from functional closure in order for core reuse to be effective," said C. Michael Chang, CEO of Verplex Systems Inc. (Milpitas, Calif.). Chang and his colleagues have devised the Tuxedo LTX system as an automated solution to achieving functional closure. Essentially, the system extracts lower-level details from previously designed IP to efficiently fit it to new technologies.
On the other side of the question is Alpine Microsystems Inc. (Campbell, Calif.), which offers a highly dense packaging system that effectively achieves the same objective as a full system-level chip, without having to merge diverse IP on the same sliver of silicon.
Along the same lines are attempts to predesign a complex SoC and save some customization capability for later. Such platform-based approaches are gaining popularity. For example, RealChip Communications Inc. (Sunnyvale, Calif.) offers predefined IP blocks that fit into a predesigned platform that is then run through standard fab lines. And eASIC Corp. (San Jose, Calif.) offers a platform that is configurable via a single programmable mask step. That approach, in eASIC's view, is the SoC version of the gate array, offering density, low cost and high performance.
Other tools and services are based on lending low-level fab expertise to the SoC designer, an approach taken by chip maker TSMC North America (San Jose). Its CyberShuttle service claims to give rapid turnaround to prototype designs.