Partitioning an ASIC design into multiple FPGAs
By Juergen Jaeger, Synopys Inc.
Programmable Logic DesignLine (02/10/10, 02:10:00 AM EST)
Most of today's system-on-chip (SoC) designs rely on field-programmable gate arrays (FPGAs) as a way to accelerate verification, start software development early and validate the whole system before committing to silicon. The FPGA may be an intermediate or, because tough economic realities cannot justify $1M+ in non-recurring engineering charges for an ASIC, initial implementation platform for the SoC design.
Today's FPGAs are large enough to contain a complex system-level design. It's practical, however, for these designs to be partitioned among several FPGAs for various reasons. For example, you may invariably need external components in your system. Also, using several smaller devices can enable a more cost-effective solution than using one big FPGA.
But, integrating your design into several FPGAs can create interesting partitioning problems, especially for larger and/or highly connected designs.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Synopsys, Inc. Hot IP
Related Articles
- Asynchronous reset synchronization and distribution - ASICs and FPGAs
- General Partitioning Guidelines for Validation of Large ASIC Designs On FPGA
- Single event effects (SEEs) in FPGAs, ASICs, and processors, part I: impact and analysis
- Addressing the new challenges of ASIC/SoC prototyping with FPGAs
- Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs
New Articles
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
Most Popular
- System Verilog Assertions Simplified
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Optimizing Analog Layouts: Techniques for Effective Layout Matching
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)