Re-Configurable Platform for Design, Verification and Implementation of SoCs (Design and Verification without Constraints)

Swapnil S, MindTree Ltd
Bangalore, India

Abstract:

We propose a new methodology flow which will allow the visual definition of a complex SoC through instantiation of parametric IP such as processors, SDRAM controllers, DMA engines, on-chip buses, peripherals, switch matrices and coherency directories, coprocessors, etc.
 
Script based automation helps in integrating any  IP with any configurations ,selects relevant and corresponding Verification IPs(in-house developed-if Design IPs are standard), uses suitable Bus Wrappers(OCP,EBI,Avalon,MicroBlaze,PicoBlaze,PIF,AXI,AHB,APB,Generic and others) and stitches all the components design as well verification(synthesizable testbench components ) together and making use of TLMs,BFM  (replacing CPUs with Master BFMs) or Process Core based designs creates an CSOC environment.

The framework reduces the time to build integration and verify the functionality-it also has the complete set up from assembler to DFT.

Introducing:

The complete flow for FPGA (Xilinx/Altera) or an ASIC with tool configurability is taken care by the automation scripts and Makefiles –which also take care of assembler and compilers (GNU, GCC).

Such IPs to be integrated are captured either at the specification level via UML, at the model level (SystemC, HDL) or at the implementation level (RTL VHDL or Verilog).

The unified environment then simulates the whole system and in the process, a near-optimal solution in terms of area, power and performance, is achieved.

The main perspective of the complete CSOC system is that it not only integrates various designs Ips but also integrates corresponding inbuilt standard VIPs (Verification IPs) that are needed to verify a SoC in real life. These VIPs sit on the same bus that is inside the SoC and share the bus with various Design IPs.

Configurable SoCs (CSoCs), consisting of processor-, memory controllers and simulation models of memories, and on-chip reconfigurable parts for customization to applications.

CSoCs combine the advantages of both: ASIC-based SoCs and multichip-board development using standard components, every time the functionality or standards are changing. Thus, besides other advantages, an enormous cost and risk minimization perspective is obvious for industrial CSoCs.

It is indeed a framework platform for –

• Computing domain, e.g. processor (time domain), dedicated ASIC-based (space domain), (dynamically) reconfigurable (time / space domain) + various memory-cores and technologies
• Specification and programming method, e.g. high-level language HLL (C, C++, SystemC, Matlab, Java, etc.),Assembler language (μC-CPU specific), hardware description language HDL (Verilog , VHDL) and   targets Multiple Applications
• Multiple Processor Core Support
  • ARM / ARC / TriMedia / NIOS / Power PC  Etc…
• Appropriate Bus Infrastructure
  • AMBA – AXI / AHB / APB
  • OCP / PLB Etc…
• Multiple Memory Configuration
  • Tightly Coupled Memories / Closely Coupled Memories (Integrated with Processor Core)
• On Chip Memory
  • SSRAM / ASRAM  - RAM / ROM Configurations
• External Memory
  • SSRAM / ASRAM / Flash (Nand / Nor) / SDRAM / DDR (I / II / III)
• Design Considerations
  • ASIC
  • FPGA
  • DFT
  • Low Power
• Support for Multiple Simulators
  • Support from all the major vendors like –Cadence,Synopsys and Mentor,
• ASIC Flow Flush
  • IP / SoC Level
  • Flow Activities
    • Synthesis
    • STA
      • DFT
      • Scan
      • MBIST
      • JTAG
    • ATPG

Implementation:

1. Processor supports

A study is done on the industry standard CPUs and what are the assemblers and compiler available –open source; so that we can go ahead and create a prototype CSOC. These are the CPUs which our CSOC support and if at any point of time Processor is changed and implemented in the CPU then by just changing the in-house built Bus Wrapper and keeping the component IPs on the Bus same we can integrate and support them.

See Appendix for the processor supports.

2. Assembly/C and GNU Tool Chain

1. Run a Perl script to generate the constrained random assembly code.
2. Assemble the generated code into a loadable memory image of the test (finite in size).
3. Run the test in the reference model to generate a golden reference result file.
4. Simulate the test using file IO to compare the results.
5. Gather coverage information to decide if iteration is needed.

Another approach for the same flow is additionally, we decided to substitute the Perl scripts that generated random assembly code with verification software written in C. In simulation, instead of loading a memory image of the test containing the random instructions, we loaded the cross-compiled verification software. While executing the software, the processor generates on-the-fly random machine code, copies it into a memory segment, branches to this segment, and executes the just generated code. After finishing the execution, it repeats this loop operation over and over again. With this approach, we are no longer limited by the size of the system memory: the software running in the device-under-test (DUT) generates and executes its stimuli indefinitely.

There is System Verilog Testbench inside the CSOC platform and System Verilog constructs are used to define and monitor the functional coverage of our design. In this way, our software can run indefinitely until it automatically reaches our coverage goal.

Hence, the verification flow is simplified to:

1. Compile the verification software into a loadable memory image.
2. Simulate the execution of the verification software indefinitely until it reaches the coverage goals.  

3. Targets Multiple Applications

Components based on the Storage domain (SATA, SCSI devices), Wireless and RF domains, networking domains have been supported .All the devices interface slots have been implemented and relevant Slave verification IPs to be integrated if needed.

4. Appropriate Bus Infrastructure

• AMBA – AXI / AHB / APB
• OCP / PLB Etc…
• Avalon,MicroBlaze,PicoBlaze,EBI
• PIF,CoreConnect,WishBone etc

5. Generic IPs

Like System Controllers and Interrupt Controllers with GIF (In-house Generic Interface that can be converted to understand any standard protocol through add on of a Bus wrapper)

6. Multiple Memory Configurations

• Tightly Coupled Memories / Closely Coupled Memories (Integrated with Processor Core)
• On Chip Memory
  • SSRAM / ASRAM  - RAM / ROM Configurations
• External Memory
  • SSRAM / ASRAM / Flash (Nand / Nor) / SDRAM / DDR (I / II / III)
• Multiple Memory Configuration
  • With / Without Patch System
  • With / Without Cache (Integrated with Processor Core / Independent)

7. Design Considerations/Verification as well

Low power domain and state machines are verified with speciality macros and classes and provision provided to be packaged and integrated with VMM from Synopsys.

8. Adaptive Verification Environment

• System Verilog / C Based Verification Environment
• Verification Platform Interface (VPI)
• Test Re-Use Methodology
• Extended HPB / LPB – I / LPB – II for Test Bench Model Integration
• System C Models and Specman e VCs can also be integrated if they come as standalone standard Verification IPs.

9. Formal Verification

Script supports for Module level Design Ips that can undergo Assertion Based Formal verification through IFV and Magellan. These IPs have been already developed and Assertion properties cover and assume properties in place –these properties can be used from the block/module level environment to the CSOC level environment to give more confidence and boost up the debugging and verification.

10. TLM and BFM based environment

Master BFMs used to replace the Processor cores to do a thorough Coverage driven verification –through in built capabilities of methodologies like VMM and OVM.

11. UML/C++ and C based environment

Uses of UML as the front end specification capture format and converting the UML to SystemC.

12. Synthesis

Scripts ready for FPGA and ASIC synthesis for DC,RC and specific to FPGAs.

13. DFT

Scan insertion and BIST related logic taken care in the complete integrated CSOC.

Conclusion:

The Methodology removes the language and processor barriers and supports integration of IPs built in any languages and creates the synthesizable Testbench components and map them within the environment   to functionally verify the SoC.The methodology also removes the barriers for CPUs to be used as one can use any of the processor cores available and creates the appropriate interconnection with the relevant IPs through interface wrappers.

References:

[1]. “ASIC Sstem-on-a-Chip”, Integrated Circuit Engineering (ICE),  www.ice-corp.com

[2] M. Glesner, J. Becker, T. Pionteck: Future Research, Application and Education Perspectives of Complex Systems-on-Chip (SoC); Proc. of Baltic Electronic Conference (BEC 2000), Oct. 2000, Tallinn, Estonia

[3] J. Becker, T. Pionteck, M. Glesner: An Application-tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing; in: Proc. of XIII Brazilian Symposiumon Integrated CircuitDesign (XIII SBCCI, ”Chip In The Jungle”), Manaus, Brazil, September 18-22, 2000.

[4] J. Becker, N. Liebau, T. Pionteck, M. Glesner: Efficient Mapping of pre-synthesized IP-Cores onto Dynamically Reconfugurable Array Architectures; Proc. 11th Int´l Conference on Field Programmable Logic and Applications, Belfast, Ireland, 2001.

[5] Y. Zorian, R. K. Gupta,: Design and Test of Core-Based Systems on Chips, it IEEE Design & Test of Computers, pp. 14-25, Oct.-Dec. 1997.

[6] B. Tuck, Integrating IP blocks to create a system-on-a-chip, it Computer Design, pp. 49-62, Nov. 1997.

[7] Xilinx Corp.: http://www.xilinx.com/products/virtex.htm.

[8] Altera Corp.: http://www.altera.com

[9] Triscend Inc.: http://www.triscend.com

[10] Triscend A7 Configurable System-on-Chip Platform – Data Sheet http://www.triscend.com/products/dsa7csoc_summary.pdf

[12] Atmel Corp.: http://www.atmel.com

[13] PACT Corporation: http://www.pactcorp.com

[14] The XPP Communication System, PACT Corporation, Technical Report 15, 2000

[15] H. De Man: System-on-Chip Design: Impact on Education

Appendix-1:

Index	Processor	Bus Interface
1a	ARM7 (ARM7TDMI)	AHB
1b	ARM9 (ARM922T)	AHB
1c	ARM11 (ARM1136 & ARM1176)	AHB & AXI
1d	CortexM1	AHB Lite
1e	CortexM3	AHB
2a	MIPS32(@24K)	OCP
2b	MIPS32(@34K) & Higher	OCP
3	NIOS II	Avlon switch fabric
4	Microblaze	LMB - Local Memory Bus PLB - (Peripheral Local us)-v46 OPB - On Chip Peripheral Bus
5	Picoblaze	PLB(Peripheral Local us)
6	LatticeMicro32(Open Source)	Wishbone
7	PowerPC(e200z0)-Freescale	Single 32 bit AMBA interface or crossbar
8	PowerPC(e200z1)-Freescale	Dual 32 bit AMBA interface or corossbar
9	PowerPC 405/440 on Xilinx EDK	Crossbar & PLB bus interconnect
10	ARC(600 and 700 families)	AHB, BVCI and also configurable to AXI
	AVR
11	Analog Devices Inc (ADI)Blackfin	Only can get our Blackfin IC's through Sales/Disti channels.
12	Analog Devices Inc (ADI)Sharc	Do
13	Analog Devices Inc (ADI)ADSP	Do
14	Analog Devices Inc (ADI)TIGER	Do
15	Trimedia(Nexperia PNX1302 )	PCI / XIO