SoC Test and Verification -> SoC complexity demands new test strategies

SoC complexity demands new test strategies
By Chappell Brown, EE Times
December 13, 2001 (10:58 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011213S0023

As single-chip systems arrive on the scene, their complexity is putting new pressure on the already strained practice of testing and verifying a design. In the past, a circuit on a single chip was simple enough to prototype and then throw over the wall to the testing department. If it didn't fly, some tweaking was probably all that was needed to move it into production.

Rapidly increasing complexity has eliminated that approach, pushing test issues into the circuit design process itself. Built-in self-test structures and design-for-test EDA tools are some of the essential recent developments in circuit design. As the test experts in this week's Focus on System-on-Chip (SoC) Test and Verification caution, designers need a smart test plan before jumping into the design process, or the results of their work could be unusable.

SoC densities have presented some new twists in this already contorted field. In a sense, it is impossible to direc tly test and verify a chip containing hundreds of millions of transistors. Sub-blocks of the design can be various memory types, microprocessors or even analog circuits. All of these may have been previously verified as part of the IP process, which is a big help, but there is still the question of how they react when combined on a single chip. On top of that, smaller wires, long global interconnect and clock skew all throw in additional wild cards. That has produced an inversion in the design process, where the cost of ATE threatens to outstrip a company's investment in design and development. More than ever, circuit designers need to head off the growing "test gap."

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