Slump doesn't ease ASIC time-to-market pressures

Slump doesn't ease ASIC time-to-market pressures
By Crista Souza, EBN
November 30, 2001 (1:54 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011130S0066

The economic slump that saw a large number of ASIC designs canceled has not lightened the burden for suppliers when it comes to delivering complex chips on tight schedules.

Production orders may be down significantly, but ASIC companies say they are under more pressure than ever to decrease time-to-market for future designs.

Some vendors say the downturn has, in fact, accelerated demand for 0.13-micron technology, which means ASIC suppliers must work quickly to validate libraries, IP, and other deliverables ahead of customer engagements. New tools and methodologies are also coming into play that compress ASIC design cycles, which can stretch out to two years for the most complex chips.

Cycle time isn't a new issue, but it has moved into the spotlight during the downturn. Recent research from Gartner Dataquest, San Jose, found that ASIC design starts this year are down as much as 20% because OEMs pulled back on product development. Yet the p ercentage of designs at or below 0.18-micron increased from 21% in 2000 to almost 36% this year, even as average ASIC complexity approached a million gates.

"The decline in ASIC design starts, which is most significant in the data networking segment, could have the effect of prolonging recovery," said Dataquest analyst Bryan Lewis. "ASIC lead times are longer [than for off-the-shelf parts]. It will take a little time to turn that back on."

Lewis noted that smaller OEMs were more likely to cancel designs, affecting some ASIC suppliers more than others. Those with a concentration of communications-oriented designs said they've felt more pressure to accelerate technology and cycle time.

"Customers, particularly in the LAN/ WAN space, are trying to design themselves out of recession, and as a result, are pushing ASIC complexity forward," said Peter Richmond, business development director at the System IC business unit of Toshiba America Electronic Components Inc. in San Jose. "The real thrust is not to cost-reduce, but to add performance and features to differentiate new systems from what [customers] have sitting in inventory."

Motivated by time-to-market

At one time, lead customers pushed the technology edge for the sake of technology, but today early adopters are motivated more by time-to-market, said Ronnie Vasishta, vice president of technology marketing at LSI Logic Corp., Milpitas, Calif.

"Time-to-market is key now, and differentiation comes down to [having] IP and services to bring products to market quickly," Vasishta said. "Our challenge is to ensure IP is available at the start of a technology release cycle to ensure the design is won."That's getting harder to do because technology is advancing so rapidly, Vasishta said.

"Design complexity has at least doubled in the last year or so, but time-to-market hasn't doubled-it's shrunk," he said. "We have to work with early process deliverables now. We can't afford to wait until the final ones are available before we start an engagement. That's a different level of risk."

A consolidated process

IBM Microelectronics has also experienced technology and time pressures from ASIC customers, so the company has focused its R&D largely on compressing the design cycle, said Tom Russell, department manager for ASIC methodology at IBM's Burlington, Vt., facility. Russell's group has been working with proprietary design tools to consolidate steps, with the goal of shaving 25% to 50% off the design cycle.

IBM is in limited pilot engagements using an internally developed tool that combines synthesis and place-and-route capabilities in one seat, a departure from the days when customers would go through the synthesis stage before handing off to the ASIC vendor for physical design.

Additionally, IBM is working to integrate commercial design-planning tools that predict early on what will happen later in the flow.

"These two different sets of innovations have caused us to rethink our engagements," Russell said. "We don 't want to create any artificial handoff points that add time and steps to the flow."

Leading-edge customers with ASIC expertise of their own may still prefer the traditional methodology, but Russell anticipates an increasing number of customers will embrace the consolidated process for its time, efficiency, and quality benefits.

ASIC suppliers and foundries are improving fab processes as well, including implementing supply chain management software that lets customers monitor their designs as they move through the fab, according to Pat Fasang, marketing manager for ASICs and multichip modules at Hitachi Semiconductor (America) Inc. in San Jose.

But such advancements are part of the natural evolution of ASIC design, Fasang said.

"There are no shortcuts; you cannot eliminate any of the steps," he said. "You can shave off some time, but for any design today, it would be unrealistic to think ASIC design [from vendor selection through RTL handoff] can be done in less than six months."