Update: Cadence Completes Acquisition of Evatronix IP Business (Jun 13, 2013)
By Michal Jedrak, Evatronix SA
Embedded.com (05/24/10, 08:01:00 AM EDT)
Today every designer faces a plethora of challenges in their SoC designs. These challenges are product release plans, design complexity, quality and goal of first silicon success. Moreover recent years have introduced a high pressure on power efficiency, not only because of mobile application prevalence, but also due to the strong community movement into the overall lower power consumption.
Today's designs are highly complex having many submodules integrated in a single chip. This brings the development to the next abstraction level where all modules need to work together smoothly and provide functionality within the scope of specification which in many cases is pretty standard. So, if they are standard, is there really a need to “re-invent the wheel” and build them in the own lab, increasing the costs and risk? Or could a good external source be used instead? IP vendors provide many state of the art modules for nowadays complex designs. These modules have many years of experience behind them, they have already been thoroughly verified and they are supported by many engineers ready to help in the race for success.
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