Platform IP for all seasons

Platform IP for all seasons
By Chris Edwards, EE Times UK
October 1, 2001 (5:20 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010928S0055

When the semiconductor intellectual property (IP) business first got underway, aside from the microprocessor cores that had already been licensed widely, engineers were concerned at how much the problems of integrating cores from different vendors together would cause them. In turn, those selling cores worried that, if they were too difficult to integrate, engineers would simply design functions inhouse.

Last year, the semiconductor IP business grew 40% to $689m, according to analyst company Gartner Dataquest. The figures for 2001 will almost certainly not be as rosy. But ARM Holdings and mips Technologies, which sit at the top of the Dataquest league table, have seen revenue growth in the first six months of this year, although mips slipped back slightly in Q2 of calendar 2001.

The fastest growing company in Dataquest's tables in 2000 was Parthus Technologies, which has steadily moved from being a design house to an IP supplier, and has become known as a platform IP provider. The company takes both third-party cores, such as the ARM7 processor, and its own IP and wraps them together in base platforms for applications such as wireless terminals and Bluetooth peripherals.

The platform model has been successful enough for other companies to adopt similar models. But the meaning of the word platform is wide enough to let it become heavily abused as a term during the next few years.

Design services

Among the new players in platform IP is Cadence subsidiary Tality, which is using its design services operation to build up a business based on IP platforms. The approach means that the Symbionics part of Tality has come full circle. The Cambridge operation's original approach was to design complete subsystems, such as Dect terminals and handsets, and then modify them for customers.

Synopsys is backing into the platform IP market through its DesignWare programme, having now brought in a degree of support for processor cores, elemen ts that were previously missing from its portfolio of bus interface and peripheral cores.

Europe Technologies in France has used the platform idea to build fast-turnaround asics and debug systems based around the ARM7 processor. Even ARM has joined the platform IP business directly, having first gone into the market indirectly through Agere Systems and Tality.

To make a platform first pick your on-chip interconnect or bus. If recent announcements are anything to go by, that on-chip interconnect is likely to be one of the flavours of Amba, ARM's name for its collection of on-chip buses. Early on in the IP business, ARM took the decision to put the specification for Amba up on its website and let other companies use it freely. Both Synopsys and Tality have adopted Amba as their preferred on-chip buses.

Strictly speaking, there are three variants of Amba overall. The first was the Amba system bus (ASB), which drew cri ticism for not being totally synchronous and therefore tricky to verify, particularly when using synthesis-based design methods.

The ASB has been superseded by a completely synchronous descendent, the Amba hardware bus (AHB). Originally a single bus connection, a new form of AHB, known as multi-layer AHB, makes it possible to form switched interconnects on-chip.

The specification for multlayer AHB was designed so that existing AHB-based cores and peripherals can plug into the switched matrix without changes to the interface. For low-speed peripherals, Amba includes the Amba peripheral bus.

On the basis that there are already many systems-on-chip (SoC) using AHB, several IP core suppliers have decided to embrace Amba entirely or at least offer it as an option. For example, ARC International and Siroyan have both picked Amba as an on-chip interconnect.

ARC is, in fact, building a bridge between AHB and its ARC tangent processor cores. The company's preferred interconnect is the Virtual Socke t Interface Alliance virtual component interconnect (VCI) as it was designed as an architectural-neutral standard. But ARC acknowledged that AHB is widely used.

Ashish Sethi, product manager for ARC, said: "We have seen that a significant amount of the IP developed in the past is Amba-based simply because it was the first one around."

Siroyan, on the other hand, has embraced Amba entirely. Its first processor implementation will use the 64bit version, but technical director Adrian Wise says the bus is designed to scale to allow higher data rates.

A similar ability to scale exists in IBM's CoreConnect, which the computer giant has touted as a standard on-chip bus for SoCs. That can move between 32, 64 and 128bit implementations. IBM has also put a switch matrix on its roadmap to boost on-chip bandwidth.

But many of the potential takers for its bus have gone with Amba, not for technical reasons but for commercial clout.

"We were looking for something that was reasonably indu stry-standard," said Wise. "CoreConnect could have filled that role but Amba looked as though it had more support." Sethi said the decision to adopt Amba came from customer demands: "CoreConnect never really came up."

Mentor Graphics, which resells some of IBM's PowerPC processor cores as synthesisable IP, has support for both Amba and CoreConnect. The company aims to use a toolset it is developing to generate synthesis files and verification suites automatically for IP cores that fit on to these and other standard buses that have bus converters in Mentor's library.

On-chip bus

Xilinx has also adopted CoreConnect as its on-chip bus for the forthcoming PowerPC-based 'system' FPGAs. Altera has decided to use Amba for its ARM and mips-based system FPGAs.

Some semiconductor suppliers have gone with alternatives, such as VCI. STMicroelectronics provided a lot of the early input to VCI, particularly the focus on automatically synthesising the connecting logic betwe en peripherals. ST has also taken on support for Amba through platform licensing deals with Parthus Technologies and, more recently, ARM.

The other 'standard' interconnect on offer is Sonics' open core protocol (OCP), based on the company's MicroNetwork architecture. This breaks away completely from the bus-based approach and turns links between cores into an on-chip network. But despite launching a website built around the concept with support for platform simulation, the company has just a handful of partners' cores available with OCP support. InSilicon and mips have agreed to provide cores with support for OCP, along with Denali and Virage with on-chip memories.

For pipelined, dataflow systems, Altera has developed Atlantic as a connection scheme. But this is not trying to do the job of an on-chip bus; it acts more as a glue for communications cores that support the huge number of bus interfaces on current comms chips, such as Pos-Phy and Utopia.

Once the bus is in place, getting the cores tog ether has become one of the easier parts of building a platform because of the third-party support that is out there for some of them. The tricky part is getting the design automation tool support right. If your customer has to bolt all that together themselves, it is probably not really a platform but a statement of intent and a bag of third-party joint marketing agreements.