SANTA CLARA, Calif. The EDA industry must step up efforts to innovate verification solutions. That was the message delivered Sept. 18 by Cisco Systems engineering vice president Andreas Bechtolsheim and Raza Foundries' Atiq Raza at a small seminar titled "Addressing Complex System and IC Verification Bottlenecks."
The two speakers, both investors in EDA companies sponsoring the seminar, held, here, said that while the EDA industry has made concerted efforts to address one of the two biggest issues in design today, timing closure, it has not adequately addressed verification the single biggest bottleneck in ASIC development.
"Design verification still consumes 80 percent of the overall chip development time," said Bechtolsheim. "The economy is slowing down, but design starts are not slowing down, so companies need tools that will make them more productive."
Bechtolsheim, who in addition to his duties at Cisco is an EDA angel inv estor, said that while the number of ASICs produced in silicon by Cisco has dropped over the last years, design complexity and the number of design starts are still increasing, raising the need for more productive verification tools.
"There has not been a fundamental productivity breakthrough in CAD in the last 10 years since Synopsys came out with Design Compiler," said Bechtolsheim. "It is time for the industry to really take a look at verification. It is by far the area that has the largest room for improvement."
Bechtolsheim called for the EDA industry to develop high-level design languages for functional verification, easier-to-use formal verification technologies and faster simulation tools. Bechtolsheim is an investor in several EDA startups, including seminar sponsors Co-design, Real Intent and Tharas.
Raza, once president of Advanced Micro Devices (AMD) and now a noted venture capitalist, said verification is a space that has many problems and thus presents many opportunities for new EDA companies.
In particular he called for tools that assist in creating architectural models.
Raza said that while he was at AMD, he advocated a methodology in which designers created a high-level functional model of a chip design, which designers would reference and design to at every level of the design process.
Raza said that the architectural model allowed 80 percent of the testing to be done up front. He then assigned a small team to code the register transfer level (RTL)."
We employed a correct by construction approach to design verification," said Raza. "RTL has to be designed by only a few people who are rigorous about their coding style."
Raza said that only six engineers coded the RTL for the Athlon processor and only two engineers coded the K6 processor. These few skilled engineers, according to Raza, did not use obscure structures allowing verification tools to handle the code more effectively and detect bugs easily. "If a block had more than 10 bugs in it, easy-to-fi nd bugs, we threw that RTL away and started the block from scratch," said Raza.
Raza, who mostly invests in silicon and systems companies, has made only a few investments in EDA companies. Most notably he is an investor in Magma Design Automation and Tharas Systems.