Socrates: Realizing the EDA360 Vision

By David Murray, CTO, Duolog Technologies

Introduction

Duolog Technologies (www.duolog.com) has been working on chip integration since 2002 and has delivered a wide range of innovative integration solutions since that time. We have continually promoted IP standardization, enhanced design quality and inter-team communications and we have by far the best integration solutions in the industry. Duolog has also developed a HW/SW integration/verification methodology that delivers an order of magnitude improvement in quality and productivity over today’s alternative solutions.

Recently Cadence Design Systems released their vision for EDA entitled "EDA360 - The Way Forward for Electronic Design" where they present an emerging focus on integration as a key solution to bridging the productivity and profitability gaps that plague today’s complex SoC products.

In this document we introduce Duolog’s Socrates chip integration platform, a hub for standards-based IP integration. By enabling high-quality design, IP reuse and high-level integration we will show how Socrates helps to realize the EDA360 vision.

Background

Originally an IP provider, Duolog also offered IP and chip design/verification services. In providing these services, we found an increasing number of customers distressed by exploding integration complexity. Rapidly expanding IP portfolios and more frequent IP reuse had become the norm. However, the infrastructures required to efficiently integrate these IP into systems were becoming prohibitively complex. Meanwhile, software development schedules were mandating earlier and more robust hardware deliverables, as well as rapid turnaround times. The traditional in-house solutions (often based on Excel and/or scripts) were simply grinding to a halt and integration bottlenecks infiltrated the design flow and chip schedules.

Duolog saw an opportunity to tackle these bottlenecks and started developing integration solutions.. By 2006, three primary solutions had been developed, that, between them, achieved full chip integration - from IP port to chip pin. These tools featured IP connectivity, HW/SW integration and I/O layer generation. By 2008, Duolog had fully committed to the EDA path and exhibited for the first time at DAC’08, where we were privileged to receive 3 best-of- DAC awards for our integration solutions based on the Socrates chip integration platform.

The Socrates platform is now in its third generation of development and Duolog continues to innovate and expand its SoC integration solutions.

What is Socrates?

Socrates is a SoC integration hub that enables rapid and robust integration from IP to chip level.

Socrates provides the following functionality:

IP Packaging and Standardization

Socrates can be used to standardize the different views of an IP, including hardware and software views. Hardware views include port, power and TLM information, and can encompass anything from I/O cells to IP components to sub-systems and even complete chips. Software views capture IP and systems from the processor perspective and include registers, memories and memory-maps. IP data is captured via the Socrates GUI, or migrated from IP-XACT, or customer-specific legacy formats. The captured data is validated to ensure design correctness and then used to generate various integration source views for design/verification and software development teams.

Hardware/Software Interface Management

Socrates manages the specification of the HW/SW interface (registers, bitfields, memorymaps and memories) and facilitates smooth HW/SW integration. Its correct-by-construction methodology promotes extensive IP reuse, guarantees consistent design views and leads to more right-first-time projects.

IP Integration Environment

Socrates provides the fastest way to integrate IP and assemble a chip hierarchical infrastructure. Socrates manages the complete assembly of a complex system from IP to toplevel, enabling design/integration engineers to deliver rapid and robust integration views throughout the design process. Socrates’ rules-based integration methodology allows massive integration efficiency and reusability, giving orders of magnitude productivity gains when compared with manual or script-based integration solutions.

I/O Integration

As well as integrating IP, Socrates manages the mapping of this integrated IP onto chip pins. Socrates supports pin multiplexing, I/O cell insertion, DFT insertion and power insertion.

Socrates also includes links to die/package flows to give a fully-automated, correct-byconstruction I/O layer, including documentation, RTL design and verification infrastructures.

Socrates can also be used as a development platform on which new or customer-specific integration applications can be developed quickly and easily.

How Socrates Enables Productivity and Profitability Savings

Socrates provides a powerful environment to standardize, centralize and synchronize design data resulting in increased quality, more design reuse, reduced schedules and enhanced inter-team communications.

1. Standardization ensures a more formal approach to design specification and reduces the number of downstream bugs through coherency checking and automation. It effectively enables a correct-by-construction methodology. Standardization not only includes the formalization of design data, but also the modelling of the data at the correct level of abstraction, thereby promoting a more specification-driven integration flow and increased design reuse. For example, Socrates can be used to capture registers and memory-maps at a high level and elaborate low-level detail such as physical addresses, reset values or read/write masks. Socrates can assemble a complex chip hierarchy, represented by tens of thousands of lines of RTL code, using just 30-40 integration rules. It can also capture pin multiplexing requirements which can be synthesized to complex power-managed, timing-aware, RTL code. Standardization also means interoperating with existing and emerging industry standards such as IP-XACT, OVM, UVM etc.
   
   
2. Centralization brings all the IP and system metadata into a central repository where it can be consolidated and verified, eliminating data duplication in the flow. The data is checked against specific design/implementation criteria to ensure design correctness. The data can be stored and managed independently, giving users more modularity and concurrency in their design. At the IP level, centralization is the key to producing integration-ready IP. At chip-level, centralization is essential to extract and communicate domain-specific chiplevel data for use in other flows. Socrates enables the extraction and presentation of domain-specific data, thereby promoting efficient and up-to-date team synchronization. br>
   
3. Synchronization leverages the captured and verified data to produce a wide variety of outputs that are used as source for multiple design teams, including IP and system-level teams, hardware & software, design and verification. This is a true correct-by-construction methodology which eliminates misinterpretation or manual translation bugs, guaranteeing higher quality designs, shorter schedules and reduced costs.
   The total cost of finding a bug is the time spent identifying, reproducing, fixing, verifying and closing the bug. The cost of not finding a bug is a lot higher. Socrates eliminates whole categories of bugs by not allowing them into the design flow in the first place.
   As synchronization is an automated process, turnaround time for incremental changes is immediate, thereby providing significant schedule savings. When using a manual process to update a register definition from a document to all its various implementation views, it can take several days for the information to propagate. With Socrates, that same process takes just seconds.

Incremental Savings Add Up

The Socrates methodology fully supports the increasingly incremental types of flow that are emerging in today’s complex SoCs. As design flows are becoming more parallel, the number of design data deltas that occur within a given schedule period are increasing. This, combined with the increase in the amount of data in the design flow (especially SW data), means that modern designs are realized as the sum of many granular design increments. Thus any savings made on automated flows (like Socrates) can be recouped several times throughout a project.

Socrates offers productivity savings of up to 50 times that of manual flows on a single project.

The Productivity Gap

The EDA360 document highlights the Productivity Gap in system development and states that design, verification, and implementation must be closely integrated. It notes that “All too often these tasks are performed in isolation with limited feedback among engineering teams.”

Productivity Management - Source: EDA360

How Socrates Bridges the Productivity Gap

• IP Standardization
  
  

  Socrates provides an environment to standardize the hardware and software views of an IP. Hardware information, such as ports and interfaces, can be ‘packaged’ to adhere to industry or customer-specific standards. HW/SW interface information can also be captured formally. All data captured in Socrates undergoes rigorous coherency checks to ensure that it is of the highest quality. This data can then be considered as single-source design intent.

• Raising the Level of Abstraction
  
  

  The HW/SW interface can be captured at a high level of abstraction in terms of registers, memory-maps and sequences. Complete sub-systems and SoCs can be rapidly and robustly assembled using “integration rules”, which abstract detailed configurability and connectivity to a more intuitive, and more productive, level. Hierarchy, for instance, is not a constraint of Socrates but an output, thereby removing a significant overhead for silicon realization. Socrates can also generate TLM views of IP/Systems to aid virtual prototyping.

• Single-source Auto-generated Views

  Socrates facilitates the generation of a wide range of source code from single-source, IP/SoC design specifications. This removes manual translation and interpretation tasks from the flow and eliminates whole categories of bugs. For example, documentation, virtual/TLM models, RTL models, OVM models and bare-metal software APIs can all be auto-generated from single source IP metadata. All Socrates generators are fully customizable to end-user flows which aids in the seamless deployment of Socrates into an existing design flow.

• Enabling Verification Productivity

  Socrates targets advanced verification methodologies such as Specman eRM, VMM, OVM and UVM. The first level of verification productivity is achieved through Socrates’ correctby- construction methodology, which eliminates translation and misinterpretation bugs from the design flow. Socrates auto-generates complete verification environments that are fully synchronized with design documentation and RTL code, eliminating miscommunication bugs. Thus, verification engineers can spend their time validating real HW/SW functionality rather than debugging manually-introduced errors due to team misalignment.

• IP Reuse
  
  

  Socrates allows designers to store IP/sub-system/SoC information in libraries and use these libraries as part of a modular approach to sub-system/chip development. The use of standard formats, coherency checks and advanced verification flows all guarantee higher quality IP. All of these factors contribute to a wider reuse of design data at both IP and chip level.

• EDA Ecosystem

  Socrates’ use of standards ensures smooth interoperability with other data, flows or tools. Socrates uses IP-XACT as a communications methodology, while still delivering a higher level of abstraction and productivity for its users. Other standard formats such as HDL, SystemC, SystemVerilog, OVM and UVM can also be output. Any emerging standards in embedded software can also be easily accommodated.

  “[Socrates] is the centre-point of our design information and is used throughout the engineering functions in the company.” SVP Product Development

The Profitability Gap

The EDA360 document highlights the profitability gap as the gap between business goals and design cost, semiconductor unit cost, and time to market (or “delay cost”).

Profitability Management - Source: EDA360

How Socrates Bridges the Profitability Gap

• Integration-Ready IP

Socrates enables the efficient creation of integration-ready IP. IP data can be formalized and qualified and, more importantly, IP views can be synchronized from a single source. This provides design teams with a complete set of synchronized and correct integrationready data.

• Fewer Bugs

Every bug has to be found, reproduced, fixed, verified and closed. With the addition of the software domain, the scope of bugs has increased and they are harder to find and resolve. Customers report that it often take a software engineer many weeks in the lab just to identify the cause of a problem, let alone fix it. The profitability gap can be bridged by eliminating the causes of bugs across the HW/SW interface. Socrates eliminates a whole category of bug in this area through the use of auto-generated register/memory-map collateral for design, verification, integration and software teams.

• Higher Productivity

As highlighted in the previous section, Socrates can efficiently bridge the productivity gap which helps to bridge the profitability gap. Socrates is the most comprehensive and efficient IP integration/chip assembly solution in the industry.

• Increased Reuse

Socrates is the most efficient and most reusable IP integration solution. Not only is reuse prolific at IP level but Socrates enables chip-level reuse. Chip-level reuse means that the entire high level central repository can be reused for derivative chips or next-generation devices. Chip-level reuse includes system memory-map definitions, IP integration rules and I/O specifications. This means that turnaround times for chip derivatives can be reduced from weeks to days.

• Early Software Development

The Socrates integration platform is a key enabler of early SW development. As well as allowing formal definition of the HW/SW interface and synchronization between all teams, Socrates also enables hardware views of the system to be quickly assembled and provided to software developers for virtual or FPGA prototyping. This is explained in more detail in a later section.

• Full-chip Integration

Full-chip integration means that the scope of integration includes different levels (e.g. from IP-level to chip-level), different system views (e.g. hardware and software) and different disciplines (e.g. design and verification). As the chip is assembled, Socrates manages the vital links between the core hardware interfaces with the die/package physical interfaces, as well as the hardware and the software views of the system.

Product Realization

EDA360 addresses product realization from IP to System:

Product Realization – From IP to System

How Socrates Enables Product Realization

• Silicon Realization

Silicon realization represents everything it takes to get a design into silicon through design, verification and implementation. Efficient silicon realization requires effective IP integration. Socrates enables fast and high-quality IP integration through the use of formalized and comprehensive IP views, and a high level of integration abstraction. Different IP views are synchronized to ensure effective and seamless team communications.

• SoC Realization

SoC realization is effectively the connecting of the silicon interface to the system. This interface is represented at the physical level by chip pins and at more abstract levels by software APIs or “bare-metal software”. SoC realization is the consolidation of packaged IP at the SoC level and this is enabled by Socrates by allowing teams to package the physical and HW/SW interfaces. Socrates can manage a specific IP peripheral port, its definition at IP level, its connectivity through the hierarchy and finally its mapping to a physical chip pin, including the type of I/O cell required, DFT requirements, as well as die and package placement. On the software side, Socrates can also create IP, sub-system, or SoC level views of the HW/SW interface and thus facilitate smoother HW/SW integration and auto-generation of the bare-metal software API.

Socrates Enables IP to System Linkage

System Realization is the development of a complete, application-ready, HW/SW platform. Socrates provides key linkages from integration-ready IP to application-ready system platforms. It provides data management and linkage from leaf-level IP to complex SoCs. The HW/SW interface can be managed from leaf level through sub-system and chip level creating a robust and synchronized view of the design. Socrates enables more efficient use of best-inclass verification methodologies such as OVM/UVM. IP data can be leveraged and linked to SoC die and package views to ensure proper physical realization. Socrates can also implement power-aware solutions including power insertion and partitioning.

Application-Driven System integration

EDA360 states that integrating IP together effectively and efficiently is a significant challenge that is not well served by the EDA industry today and, as a result, some companies report that IP integration can cost more than twice as much as it costs to buy the IP in the first place. Another issue faced is that the HW/SW interface is one of the most likely places for bugs to occur. When they do occur, it can be very difficult to determine whether they came from the hardware, firmware, software, or application

How Socrates Enables Application-driven System Integration

Socrates standardizes IP and provides an efficient IP integration environment. Utilizing this standardization, Socrates can very efficiently weave IP together, using rules-based integration, to create complex systems. The user specifies integration rules at a high level of abstraction, using powerful assembly instructions. These rules are then synthesized to produce a fully-connected infrastructure. The following diagram illustrates the levels of abstraction in this methodology:

Socrates Rules-based Integration: Raising the level of integration abstraction

By providing a high level of abstraction, users can quickly assemble a system in a formal but flexible way. Within this methodology, even the integration rules are reusable - so much so that the insertion or deletion of an IP into a system can be achieved with small incremental edits, or no changes at all depending on how the rules have been written.

In the following example, 24 integration rules, containing 166 integration instructions, are synthesized to over 5,000 lines of RTL infrastructure code.

Socrates has been used to integrate sub-systems, fabrics, FPGAs and full chips and offers extremely high levels of productivity and reusability. The Socrates methodology promotes reuse of both the IP and the system integration rules.

In addition to this rapid IP integration methodology, formal definition and synchronization of the HW/SW interface means that robust software development platforms can be provided earlier in the flow. This is explored in more detail in the section entitled ‘Early Software Development’.

Application-driven system verification

EDA360 notes that software verification and debug are equally as time-consuming as hardware verification. It states that a lot of verification is required on analog/digital and HW/SW boundaries and that the solution employs a more holistic verification flow. It envisions the possibility of bringing traditionally hardware-centric, metric-driven verification methodologies into the embedded software world.

How Socrates Enables Application-driven System Verification

Socrates generates verification source (e.g. SystemVerilog/OVM/UVM) for HW/SW verification and allow verification engineers to quickly ramp up in IP and system verification. Also, verification engineers are less likely to become the victims of misalignment bugs or the finders of misinterpretation or translation bugs. In essence, they are freed up earlier to find real bugs in the design itself, rather than in the verification environment.

The Socrates roadmap continues to raise the level of abstraction as it aims to increase the scope of coverage between hardware, software and verification views.

Early Software Development

The EDA360 vision focuses on getting software applications up and running, as soon as possible, on a hardware/software platform that meets user requirements. Methodologies that enable early software development include virtual prototypes, emulation and FPGA prototyping. Socrates also makes significant contributions to early software development.

How Socrates Enables Early Software Development

• Socrates provides a single-source HW/SW definition which can be synchronized across different views. This HW/SW definition is rigorously checked to ensure functional correctness. From this, documentation, virtual prototypes, RTL code and HVL code is auto-generated, thereby synchronizing all of the teams. Not only does this enable a quick turnaround time for incremental changes to the design intent, but the auto-generation eliminates misinterpretation or miscommunication bugs. This is explored in more detail in the section entitled ‘Enabling Integration-ready IP – Keeping Teams Synchronized’.
• Socrates guarantees the quality of the HW/SW interface by producing verification packages such as Specman ‘e’, VMM, OVM, or UVM to test the interface. Enabling this advanced verification at the RTL level ensures the removal of many HW/SW integration bugs and thus enables faster and more robust FPGA prototyping.
• Socrates auto-generates TLM Views to enable virtual prototyping. As few as 12 IP registers could require up to 1200 lines of SystemC code for modelling purposes. With Socrates, this code is auto-generated in a correct-by-construction manner.
• Using rules-based integration, emulation/FPGA prototyping flows can be delivered quickly and with high quality, giving SW developers early design snapshots. Incremental releases can be delivered to software developers as the SoC integration process continues and the SoC matures.
• Socrates can also help with HW/SW debug by automating the insertion/integration of monitor logic into a design, and routing monitor signals across the hierarchy. It is also possible to ‘dis-integrate’ an existing design and produce a build for quicker compile and debug cycles. In fact, Socrates can produce multiple RTL builds from a single source and have these available for software developers as debug builds.

Enabling Integration-ready IP – Keeping Teams Synchronized

EDA360 proposes a new paradigm in IP development with the introduction of stacked IP – the integration-ready IP. This IP includes everything from below OS to hard IP silicon. Therefore, this new style IP development team comprises multiple disciplines in potentially diverse locations. There are many challenges to delivering an environment where such diverse teams can work effectively together.

“Design, verification and implementation must be closely integrated. All too often these tasks are performed in isolation with limited feedback among engineering teams” - EDA360

Consider the two main bug sources in such a flow:

• Misinterpretation bugs occur if designers need to manually translate design intent to their source view.
• Miscommunication bugs occur if design intent changes without proper synchronization between the different teams.

The following factors contribute to a significant increase in these bugs:

• Concurrent development is becoming the norm for complex SoC design. This leads to a design flow with many different increments, increasing both misinterpretation and miscommunication bugs.
• Design intent may iterate between teams as a design is realized. This leads to grey areas regarding design intent ownership and communication.

In fact, a customer recently confided that over 70% of the bugs in their design flows could be attributed to miscommunication.

The key metric for any proposed solution in this area would be the number of misinterpretation and miscommunication bugs that can be removed. Socrates has been proven to eliminate these categories of bugs from IP/Chip developments. Socrates enables the efficient development of integration-ready IP by promoting a more data-centric development process, where single-source design intent is formalized and centralized and from which source data is generated for the diverse teams.

Case Study: Managing the HW/SW Interface of a Complex Multimedia Chip

This example is taken from a case study on managing the HW/SW interface of a Texas

Instruments OMAP platform. The following process is used:

1. Capture high-level register definitions using Socrates.
2. Check and guarantee correct register definition.
3. Generate different team views.
4. Maintain team synchronization.

From a single-source specification, Socrates generated source code for a wide range of design and verification teams. The following results were noted:

The SoC platform comprised 5 processor subsystems and 169 unique IPs (253 instances in total). The HW/SW interface comprised 7,991 registers with a total of 36,105 Bitfields. The system had 8 levels of memory-map hierarchy. Socrates was used to manage all aspects of the HW/SW interface.

The following HW/SW interface collateral was auto-generated from Socrates:

• 94 MB of HW/SW Documentation (2 flavors)
• 7.5 Million lines of C Code, (3 flavors)
• 1.26 Million lines of Specman ‘e’ code (2 flavors)
• Millions of lines of IP-XACT

Socrates managed the HW/SW interface from IP to chip level and kept all teams in sync.

Socrates – The Integration Hub

Socrates, in addressing integration challenges, becomes a central hub though which all design data flows. The benefits are significant productivity and profitability leaps. The following is an illustration of just some of the data flowing through the Socrates hub and the teams who benefit from it:

Socrates can be viewed as a front-end data management environment. All design data flows through the hub, is validated, and all output views are then generated from the hub.

Conclusion

In summary, Socrates realizes much of the EDA360 vision, bridging customers’ productivity and profitability gaps. Projects employing Socrates use fewer resources, have these resources communicating more effectively, have fewer bugs and have more predictable deliverables.

Duolog has been focused on chip integration for several years and is currently developing the third generation of its award-winning integration technology. Socrates, through its Standardize, Centralize, Synchronize methodology provides an efficient environment for SoC realization, greatly enhancing customer productivity, profitability and predictability.

The EDA360 vision highlights the importance of integration as an enabler for efficient system realization and the challenges facing integrators. Socrates answers these challenges.

Socrates Realizes the EDA360 Vision