By Bipin Patel, eInfochips
edadesignline.com (June 02, 2010)
Selecting verification methodology that allows maximum reusability within a project is very important to complete verification within the defined timeline. If we fail to choose an appropriate methodology then there are possible chances of work being duplicated at different levels of the verification process in the same project, which is nothing but a waste of time and resources.
Thinking through the process of selecting a verification methodology needs to take into consideration the various levels at which we need to do the verification and how verification environment (VE) components from bottom to top level (block to chip) verification can be directly or indirectly reused with no or little modifications. This can help a lot and save significant time during the verification cycle.
A monitor-based verification approach is an efficient way to make many VE components reusable within the same project and to keep the environment more simple and similar across various levels. One can easily understand the flow, and any newcomer can ramp up his knowledge in a short period of time, and can start working on any module of a complex chip if the approach is common for the entire team in any verification project.
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