System specs key to SoC success
By Michele Borgatti, NVM-SoC Design Manager, Non-Volatile Memory Design Platform, Central R&D, STMicroelectronics, Agrate Brianza, Italy, e-mail: firstname.lastname@example.org , EE Times
September 14, 2001 (2:20 p.m. EST)
A major cause of failure in the design of silicon systems is incorrect or ambiguous specification. It is necessary to capture system specifications in an executable, unambiguous format in order to achieve agreement early on in a concurrent hardware/software design process between customer/provider and the various design teams.
Our approach is to define the system first, then establish the implementation (hardware and software partitioning) later in the design process. This has a dramatic improvement in the system-on-chip (SoC) development cycle time.
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At STMicroelectronics (STM) Central R&D, we decided to implement a system-level design flow based on hardware/software co-design, architectural exploration and inte llectual-property (IP) reuse. We explored the CoWare N2C (Napkin to Chip) methodology and design flow with a pilot project: the design and implementation of a single-chip SoC speech-recognition system.
The first prototype system developed during 1999 comprised a voice-activated controller with built-in speech-recognition capabilities, and implemented a fully hardwired STM-proprietary novel algorithm. Built with a 0.25-micron ASIC, it used external nonvolatile memory to store word templates and parameters. Although this first prototype showed very low power consumption and interesting recognition performance, it could not be mapped easily into an SoC.
To improve the flexibility of the recognition system and to use embedded flash memory, the main processing functionalities have been reorganized as hardware coprocessors integrated around an ARM7TDMI 32-bit microprocessor and a 2-Mbit embedded flash. A set of peripheral IP also had to be included (USB, I2C, etc.).
The main goals of the So C project were:
- Investigate a top-down design methodology through hardware/software co-design;
- Achieve first-time design success through a design methodology that synthesizes correct-by-construction hardware/software interfaces;
- Make use of design reuse and socketization of highly parametric functional blocks ;
- Exploit architecture exploration to drive specs definition for embedded flash memories;
- Use hardware emulation for register-transfer-level (RTL) sign-off.
A full C/C++ description of system functionalities and test benches and a handful of complex IP blocks described in VHDL-RTL were inherited from previous projects. In parallel, the main IP blocks devoted to speech processing were completely redesigned and generalized as highly parametric IP.
A functional model in C/C++ of the speech-recognition application was developed starting from the original code. This phase of the project included a significant generalization of the functional blocks of the systems since the original specification was written with a fully hardwired implementation.
Both pure functional (untimed C) models and encapsulations of VHDL models were provided. Communication details were removed in functional models, providing a complete separation between functionality and communication. This allowed fast- turnaround evaluations of different hardware/software partitions of the system.
The system-executable specification was evaluated in a multilevel simulation through top-down model refinement. Intermediate-level simulation that is cycle-true for software execution and fairly untimed for hardware was used to evaluate the performance of a candidate system hardware/software partition early.
The main voice-processing modules were available as parametric VHDL IP and recoding in RTC was not necessary. The resulting mixed N2C, ISS and VHDL simulation could not be used for extensive simulations.
We used N2C-generated VHDL code to integrate the full VHDL RTL description of the chip. Hardware emulation was used for RTL sign-off. The overall effort required two man-years.
The speech-recognition SoC achieved a successful tapeout and was first-pass 100 percent functional. The chip includes 300,000 gates of logic with about 5 million transistors.