By Sriram Balasubramanian, Srikanth Vadanaparthi, Sayandeep Nag, Chandrashekar BU from Synopsys (India) Pvt. Ltd,
Low power technology has its genesis in battery powered portable applications. With the recent worldwide focus on green technologies it has started impacting even non-portable applications. With studies showing that the installed base of semiconductors worldwide contribute more to global warming than the entire airline industry, pressure on appliance manufacturers to reduce power consumption/dissipation is very high. The mandate to power-rate  appliances only adds to this pressure. This in turn translates into low power requirements for the semi conductor devices that go in to make these appliances.
Connectivity standards such as USB, PCI-e, and Ethernet are ubiquitous in usage and applications. With laptops, mobile phones, and derivative devices such as PDAs becoming widespread, the focus on battery life is very intense. Most devices have one or more ports with the above connectivity standards.
Because these ports are all not used simultaneously and have a bursty usage model, there are opportunities to save power when the ports are not in use. This gives rise to the need for low power mode of operations.
There are various degrees of low power modes, such as:
- Complete power off
- Partial power down, and
- Clock gated mode.
Each mode results in varying degrees of power savings and many devices allow applications to control power saving based on the context in which the device is operating. The choice of mode depends on various factors such as the amount of power savings required to the minimum recovery time to wake up and resume normal operations.
Until recently, most semiconductor devices supported low power mode using clock gating. In this mode, the clock portions of circuitry that is not required for functioning. These portions would get switched off thus saving dynamic power. However, the clock gated logic still consumes leakage current. While this was insignificant in earlier >90nm technologies, these are quite significant in the deep submicron technologies. Because leakage power has become a regulatory topic under green technologies, the focus is to reduce it as well. This resulted in the need to optimize power distribution completely to portions of the device during idle modes. More advanced techniques such as multi voltage design practice, power gating, back bias, multi-rail retention , and so on were developed. Standards such as Link Power management (LPM)  on USB came into existence.
II. FOCUS AND ORGANIZATION
This paper focuses on the verification challenges and the methodology used to verify a low power design that embeds a combination of techniques to save power.
The authors have used the following power savings techniques on the High Speed OTG (HS-OTG) controller:
- clock gating,
- dynamic clock switch over to lower frequency and
- power gating techniques
This power gating techniques (henceforth referred to as hibernation) brings in significant power savings to the core.
The verification involved functionality before, during and after the hibernation state, measurement of dynamic and leakage power during the hibernation state, and benchmarking the resume time duration.
This paper is organized as follows:
- Section III- Overview of the USB standard and the provisions in the standard for potential power savings.
- Section IV - Overview of the Hibernation feature in the current implementation of the HS-OTG product.
- Section V - Detailed information on the verification methodologies used, which is the primary focus of this paper.
- Section VI - Conclusion and References.
III. USB STANDARD – BACKGROUND AND POWER SAVING FEATURES
The Universal Serial Bus (USB) standard came into existence primarily as an easy to use interconnect mechanism between the PC and various external peripherals such as the keyboard, mouse, memory sticks, PDAs, camera and mobile phones. It is a fast, bi-directional, isochronous, low-cost, dynamically attachable serial interface that is consistent with the requirements of the PC platform of today and tomorrow. While the early versions of the USB standard could support relatively slow speeds of 1.5Mbps, later it was upgraded to 12 Mbps and 480 Mbps (USB 2.0). The recent USB 3.0 standard supports super high speed data rates of the order of Gbps.
The USB 2.0 network primarily works on the host-peripheral architecture. Because the USB provides full support for real-time data for voice, audio, and video, it began to be used for connecting many portable devices. With the advent of digital cameras and portable printers, the requirement to connect a camera directly to printer to print photographs became evident.
The USB OTG (On The Go) standard developed as a result of this need. USB OTG uses the following protocols to provide additional functionality:
- Host Negotiation Protocol (HNP): Enables dynamic host/peripheral capability and role reversals
- Session Request Protocol (SRP): Enables a peripheral device to attract the attention of the host and start a new session (even when the USB Bus Voltage (VBUS) is powered off).
There are restrictions on power usage imposed on devices. Devices on USB can either be self-powered or bus-powered.
Self-powered devices may draw up to 1 unit (100 mA) load from the bus and derive the rest from an external source. The 1 unit load allows detection and enumeration without external supply (but not complete USB operation).
Bus-powered devices draw power from the VBUS. They are classified as low-power and high-power devices. In low-power bus-powered functions, the device cannot draw more than one unit load (100mA) from the VBUS. In high-power bus-powered functions, the device cannot draw more than one unit load (100mA) from the VBUS until it has been configured. After the device has been configured, it can draw a maximum of 5 unit loads (provided it requested it in its descriptor).
The USB standard also provides for a suspend mechanism allowing select devices to be entered into suspend state thereby reducing power consumption.
The original suspend and resume mechanism in USB OTG used to be time consuming. However, the USB standard later introduced a new state called SLEEP, wherein entry and exit is faster through the Link Power Management (LPM) feature. This allows for more granular power saving states that can be used by a designer. For inter-chip devices that do not require long USB cables, two new standard additions are available to reduce power consumption:
- IC-USB for FS/LS devices and
- HSIC for HS devices.
Inter Chip-USB (IC-USB) uses several voltage classes ranging from 1.0V to 3.0V to support different industries and technologies. The lowest host-device compatible voltage class is negotiated to achieve maximum power savings. Incremental power saving is achieved by controlling data line (D+/D-) termination resistors while USB traffic is in force. The switches controlling the connection and disconnection of the pullup-pulldown resistors are managed at the hardware level independent of the USB software stack.
High-Speed Inter Chip (HSIC) interface uses source synchronous clocked serial interface where no power is consumed unless there is a data transfer. It removes chirp protocol, thereby saving some more power. The FS/LS logic can be removed from the controller and the PHY can also be smaller because analog transceivers are not required. However, most of the power savings is really because it uses 1.2V LVCMOS signaling on Strobe/Data as compared to 3.3V signaling on D+/D- lines.
USB3.0 has achieved further power savings but that is not the scope of this document..
Overall several USB-IF standards initiatives have been taken up aggressively for minimizing and negotiating power drawn on the USB bus.
IV. HIBERNATION FEATURE IN HS OTG CORE – THE POWER SAVINGS CONCEPT
The USB standard  provides the hooks for such features such as VBUS off, Suspend and Sleep , which facilitate power savings, but the exact method to implement the power savings in the USB devices was left to the ingenuity of the designer.
Clock gating is the most basic power saving method. It involves switching off the clock for those portions of the device that are not functioning at a given point.
Another variant of this mechanism is to switch to a low frequency clock when the device is in idle mode. While both methods save dynamic power to a certain extent, there is an insignificant amount of leakage power still getting dissipated.VDD cut off methods, multi-VDD designs, and multiple power rails help address this issue.
Typically the VDD cut-off method switches off the power supply  to those portions of the circuitry that need not be functional while idling.
Such portions of the circuitry that are switched off are said to be hibernating. In such systems, there is still a small portion of the circuitry that is awake and waiting for a session start intervention either from the application or from the remote device to which it is connected. Such blocks are called Always-ON blocks. When the always-ON block detects the need to wake up the hibernating portions of the circuitry, the states of the latter are restored immediately after power up so that they can continue to work from where they left off. Thus before entering hibernation, it is imperative that the key states of the hibernating block be stored in what is called as retention registers and after wake up restored.
The USB standard includes provisions for power savings through suspend, Sleep, and VBUS off. Each state requires a different method of power savings. This is because the response time to wake up and continue working is different in each case.
Thus in a SLEEP state (from which the recovery response requirements are stringent) is more amenable to clock gating of those portions that need not be functional and switching to a lower clock frequency mode for those that are functional.
An IDLE state provides more possibility of power savings through VDD cutoff for the major portions of the circuit, with a small portion known as the Always-ON block working on a slower frequency clock.
Accordingly, the USB HS-OTG core is designed for a combination of dynamic clock switching, clock gating, partial power down, and hibernation in order to save power .
When the USB port is suspended or placed in sleep state, the Controller Places the PHY in a mode that draws minimal power from supplies and also shuts down  all blocks not required for Suspend/Resume operation.
To further reduce power consumption within the MAC Controller, clock gating and partial power-down modes (when the USB bus is suspended or the session is not valid) are employed.
In the Partial Power down mode, you can choose to turn off power to some of the OTG Controller modules.
In the clock gating mode, one can choose to gate the select clocks to some of the OTG Controller modules.
V. LOW POWER VERIFICATION
While the size of the Always-ON module / power management unit may be small, it has its effect in almost everything the core does. Thus the power management scheme verification has to be integrated to the functional verification of the core. At a minimum, the core must be proven to work in all its power state modes and also deliver the power savings that it has been designed for. The verification must also ensure that the core is able to transition from one mode of operation to another – modes in question in this case are:
- fully functional,
- partial power down and
- maximum power down modes (idle);
The design must respond appropriately to stimuli and go through the correct state transition sequences. Thus the notion of coverage to include power savings mode and the need for assertions and other testbench infrastructure to cover power management becomes important. Ordinary simulators used for verification do not typically model VDD cut-off; voltage aware simulators are required.
The power aware verification must check for the following types of errors:
- Incorrect application of voltages/ unplanned voltage states,
- Voltage scheduling errors,
- Power on reset sequences,
- Voltage monitoring and handshake logic errors,
- Logic conversion errors,
- Memory corruption and
- Voltage race errors.
The testbench infrastructure and assertion based checks need to be revised for the effects of the power management.
To verify all the power states in Hibernation power management scheme, the complete randomization environment methodology does not cover the required verification space. A robust methodology is required in which the initialization sequence and transfers are randomized and the power management sequence is not randomized (i.e. directed). Ideally this methodology should verify two fundamental properties of design:
The power down system internal signals must have a value of “X” when it is switched OFF. The normal RTL simulator cannot perform this kind of checks. To do this, a Voltage aware simulator such as MVSIM tool can be used. The voltage aware simulator requires power management information of the complete DUT as Input in standard power format (i.e. UPF) or tools readable format.
It should be checked that the power down system must be switched off when needed and is getting powered up only when needed, i.e. ensure that there are really power savings happening. Figure 1 illustrates the block diagram of the testbench used for the verification of the HSOTG core.
Figure 1: Testbench block diagram
Figures 2 and 3 illustrate sample application driver sequences that are required to program the device into power down mode.
Figure 2: Device mode Suspend and Resume partial power down with lower frequency (32 KHz) clock enabled
Figure 3: Device mode Suspend and Resume with clock gating
The following verification space must be covered for Hibernation power management feature:
- Entering Power Down State: The application driver needs to store all the essential registers before switching off the system, so that when it is powered up it can come back to the same state. When the system is powered on, the Always-ON unit consumes minimal power until it is enabled to perform required tasks by using clock gating techniques, write some checkers on clock signals for transitions in the Always-ON Unit. It must be ensured that the clocks to the power down system are OFF before entering the power down state. Checkers have to be written on the clock signals to make sure they are switched off.
- In Power Down State: In the power down State, the interrupts must come only from the Always-ON block / Power Management Unit. Checkers have to be written for the interrupt lines coming out of power down system to check that there are no transitions on it. The internal signal values of the power down system must be “X”.
- Exit from power down State: The Always-ON unit informs the application driver when to power up the system based on events from the remote device. The Application driver then restores the essential registers and waits for the system to exit the power down state gracefully. The Always–ON unit handles all the events until the power down system exits the power down state.
The above sequence must be verified in handshake with the hardware and test bench infrastructure. To ensure that the device has indeed exited from power down state gracefully, you must wait for all the required interrupts, read all the registers to check the read values are according to the specification, and also perform random transfers to ensure the device is capable of handling all kinds of transfers after power down state.
The HS-OTG test environment that was used for verification was an HVL-based constrained random environment that used embedded automated functional coverage. The HS-OTG core already had a randomized verification environment. It required enhancements to update the OTG controller drivers to initiate the power saving mode. Randomization was brought in terms of when to enter and how to exit the power down modes. Assertions were used to check the relevant power mode entry and exit control signals.
This functional verification covered the following power management aspects of the core:
- State retention
- Shut-down sequence.
- Always on Blocks
- Wake up sequence
- Fully functional power state
Initialization: In a power-aware verification, initialization is used to load memories, set constants, and set the simulation length. Thus if the initialization block is used for blocks that are off by default and wake up later, the actual initialization process must be deferred until the actual wake-up. In addition, memory initialization must be repeated after every power up. Therefore, it is important to have the tests cover the hardware-based initialization sequences.
State retention: When a power domain goes into shut-off state, there are save/ restore registers  associated with this state that retain and later restore the state values when it is powered up again. It was necessary to verify that all necessary registers were saved and that it was possible to restore them to the original state after powering it on again.
Shut-down sequence: The sequence in which the shut down has to be executed had to be verified.
Always-On Blocks: The verification covered the functionality of the Always-On blocks, which perform the bare minimum functionality during the power down state, until either the user intervenes or the remote device interrupts, seeking a Power-On.
Wake up sequence: Once the system was powered on, the following was verified:
- The exact sequence in which the wake up must occur to bring the powered off block to its original state and
- The handover of control from the Always-On block to the newly powered on block.
Fully functional power state: Once powered ON and the original states are restored, it is necessary to verify that all the original functions are working properly as it was before it went to the power saving mode. So the transfers were restarted.
Role of CRV: As can be seen from the different aspects that need to be covered in order to verify the Low Power design, the number of possible scenarios related to getting into power down state and later waking up and continuing as before is enormous. This is where the concept of randomization helps. An HVL-based constrained random verification was used to verify the core. In order to cover as many scenarios as possible and for the ease of debugging, it was decided to run short simulations with multiple seeds.
The following tools were used:
- SYNOPSYS VCS,
- VERA based environment,
- SYNOPSYS MVSIM for the verification activities and
- IC compiler for Synthesis.
This document describes the challenges and a workable methodology for verifying low power modes in complex systems. The intention was to have a phased approach which will be useful to verify low power systems right from the application programming sequence to the correct functionality of the power management unit. Our next task is to focus on the application of multi voltage simulators and the usage of VMM based flow to perform the verification of low power functionalities.
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