Hybrid integration: Production ready
Hybrid integration: Production ready
By Axel Reisinger, Senior Scientist, Mani Sundaram, Vice President, Optoelectronic Technology, TeraConnect, Nashua, N.H., EE Times
February 20, 2002 (6:49 a.m. EST)
Those looking to produce optoelectronic devices for use as high-speed, high-bandwidth optical interconnects have three possible technology choices. Direct fabrication of these devices from compound semiconductor substrates is possible, but it would appear to provide the least likely avenue for timely and successful development. Instead, the techniques of monolithic or hybrid integration of compound semiconductor devices on silicon substrates appear to be the most promising process routes to these devices.
While monolithic integration has been plagued by seemingly insurmountable problems over a long development history, research efforts continue. More important for immediate needs, however, is the recent demonstration of production-ready hybridization technology for two-dimensional optoelectronic laser and detector assemblies that can be used in the fabrication of high-speed optical interconnects.
Tests of products using arrays of verti cal-cavity surface-emitting lasers (VCSELs) bonded to an ASIC in a 4 x 12 configuration have demonstrated high signal integrity, performance and reliability. Equally important for OEMs, the hybridization approach uses low-cost silicon and enables efficient, proven microelectronic manufacturing pro-cesses supporting high-volume manufacturing.
Ideally, the simplest and most direct manufacturing route for VCSEL-based optical interconnects is one in which the electronic and optical components are integrated on the same substrate. Since the VCSEL cannot be manufactured in silicon, this integration could conceivably be accomplished with gallium arsenide (GaAs) or indium phosphide (InP) substrates.
However, there are taxing problems with both of these substrates. Neither of these compound semiconductors is physically robust and the substrates are difficult to handle. Their inherent brittleness has limited wafer sizes to 150 mm for GaAs and 100 mm for InP. This size limitation constrains the through put of wafer-processing lines treating these substrates, and the substrates' fragility affects yields, increasing manufacturing costs further.
Fabricating electronic devices based on compound semiconductors is inherently more complex and more expensive than using silicon, due to fundamental process chemistry. It is easy to grow an insulating oxide on silicon-enabling the creation of the "metal-oxide" portion of a metal-oxide semiconductor (MOS) structure simply by adding oxygen and heat. The inability to grow an insulating oxide on GaAs or InP has made it difficult for these III-V compounds to compete with silicon in the cost of manufacture.
The silicon process is simple and mature. Device processing on compound semiconductor substrates, on the other hand, requires additional deposition and delineation steps. The availability of surface sites of different chemical reactivity (that is, Ga or As; In or P) on compound semiconductor substrates further complicates the reactive-chemistry possibilities in device fabrication processes.
To minimize manufacturing costs, many in the industry visualize a compromise route for the manufacture of integrated VCSELs and other compound semiconductor devices, where the silicon-based electronic driver circuitry and GaAs-based optoelectronic components are both integrated on a silicon substrate. This process technology circumvents the difficulties associated with the compound semiconductor's chemistry-the electronic circuitry is fabricated in silicon using standard silicon-based process technologies-as well as its physical fragility: The hybrid system has the physical robustness of the substrate silicon. However, despite massive research efforts over the past two decades, this approach has yet to achieve a successful production application.
The main difficulty with the manufacturing protocols for such structures is the necessity for heteroe pitaxial growth of GaAs on silicon. The 4.1 percent mismatch between the lattice parameters of silicon and GaAs presents a formidable challenge for the direct growth of defect-free GaAs on the silicon. A comparable lattice mismatch exists between the crystal structures of InP and silicon and would most likely cause high defect levels in hybrid structures of an InP-on-silicon approach.
This lattice mismatch is the primary physical cause of the lack of success in efforts to produce a manufacturable GaAs solid-state laser on silicon, since ultralow defect densities in the compound semiconductor layers are a prerequisite for successful laser fabrication.
Many routes for reducing these defect levels have been tested, ranging from placing a variety of buffer layers between the silicon and the compound semiconductor, through employing off-axis, stepped-silicon surfaces as lattice-matched starting surfaces for the heteroepitaxial process.
The most recent r eports have described promising results using strontium titanate as an intervening lattice-matching layer, but successful production applications have not yet been tested. A review of the current literature suggests that monolithic integration of GaAs or other compound semiconductors on silicon may be years away from successful production applications.
A more promising solution is the use of physical rather than epitaxial hybrid structures. In this case, the compound semiconductor-based VCSEL chips would bond to a silicon chip that contains the necessary electronic driver circuitry for the VCSEL. Recently, developments in the fabrication of two-dimensional arrays of VCSELs combined with improvements to flip-chip bonding methods have yielded promising hybrid devices.
One example is a 48-channel transmit module realized by hybridizing a 4 x 12 VCSEL array to a silicon germanium ASIC. Each channel operates at 2.5 Gbits/second for a total bandwidth of 120 Gbits/s. The VCSEL arrays show excellent reliability and scalability, and lower manufacturing and deployment costs than similar devices produced using single-dimension arrays. Array size can be scaled to accommodate increases in bandwidth requirements. This type of integrated device, in contrast to those requiring heteroepitaxial process technology, is ready for immediate production use.
Using flip-chip hybridization, two-dimensional optoelectronic (2DOE) integration can provide a high-speed, high-signal-integrity electrical interface between a VCSEL array and a matching array of laser driver amplifiers in the driver ASIC. In the 2DOE receive module, a similar use of flip-chip hybridization and solder-bump bonding provides an interface between a PIN diode detector array and transimpedance amplifiers. Such a hybridized 2DOE chip results in a compact optical engine that conserves board space while maintaining high signal integrity.
The successful fabrication of these devices has its roots in the technology of focal plane arrays for infrared detectors, a natural pathway for producing the dense planar VCSEL arrays, and in advanced solder bump technology.
Copyright © 2003 CMP Media, LLC | Privacy Statement