Shawn McCloud, Product Line Director HLS, Mentor Graphics
EETimes (7/21/2010 8:04 AM EDT)
As the manual RTL design flow stumbles under the burden of titanic designs, an excessive burden is placed on RTL verification teams to meet expectations for design cycle time and quality of results (QoR) in the hardware design flow. If not lifted, this truly Sisyphean endeavor will eventually sap the drive of the electronic design industry because verification is the bottleneck of modern design flows.
Instead of prolonging the painful process of finding numerous bugs in manually produced RTL code, EDA tool flows should provide relief by creating bug-free RTL designs through high-level synthesis (HLS) tools. This is not simply an exercise in utopian logic; an increasing number of RTL engineers demand it. A recent blind, worldwide survey found that verification is the primary reason for using high-level synthesis, because HLS makes it faster for engineers to verify their designs when compared to a more error-prone manual RTL implementation process.
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